IP Library Granted Patent US 7,256,105
Granted Patent B2
US 7,256,105 · App. 11/120,108 · Granted Aug 14, 2007

Semiconductor substrate and thin processing method for semiconductor substrate

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Quick Facts
Patent No.
US 7,256,105
App. No.
11/120,108
Granted
Aug 14, 2007
Kind
B2
Abstract

A semiconductor substrate having a first substrate surface which includes a device area in which semiconductor devices are formed and a substrate peripheral portion which does not overlap with the device area. A concavo-convex portion is formed in the substrate peripheral portion. Preferably, a concavo-convex portion is formed in a side portion which adjoins the peripheral portion. The concavo-convex portion formed in the substrate peripheral portion or the side portion may be formed by a method such as dry etching, wet etching, mechanical grinding, electrolytic plating, nonelectrolytic plating, or patterning using one of a resin material and a metal material. A thin processing method includes forming the device area; forming the concavo-convex portion in the substrate peripheral portion; adhering the first substrate surface to a support; and grinding a second substrate surface of the semiconductor substrate, which is opposite with the first substrate surface.

Claims (10)

1. A method for thin processing a semiconductor substrate, comprising:

forming a device area on a first substrate surface of the semiconductor substrate, wherein semiconductor devices are formed in the device area;

forming a concavo-convex portion in a substrate peripheral portion which does not overlap with the device area in the first substrate surface;

adhering the first substrate surface to a support; and

grinding a second substrate surface of the semiconductor substrate, which is opposite with the first substrate surface.

2. A method as claimed in claim 1 , wherein the adhering of the first substrate surface includes adhering the first substrate surface via an adhesive layer.

3. A method as claimed in claim 2 , wherein the adhesive layer is in a fluid state.

4. A method as claimed in claim 1 , wherein the grinding of the second substrate surface is performed by back grinding.

5. A method as claimed in claim 1 , further comprising:

reducing a diameter of the semiconductor substrate by grinding a side portion of the semiconductor substrate device area, so that the diameter of the semiconductor substrate is less than a diameter of the support.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: SEIKO EPSON CORPORATION
To: ADVANCED INTERCONNECT SYSTEMS LIMITED
Reel/Frame 044938/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2005
From: YAMAGUCHI, KOJI
To: SEIKO EPSON CORPORATION
Reel/Frame 016533/0303 →