Decision feedback equalizer design with interference removal and reduced error propagation
View Patent ↗A method for designing a decision feedback equalizer (DFE) that handles packet based input data signals uses an inter symbol interference (ISI) removal loop and an inter chip interference (ICI) removal loop which is nested inside the ISI loop, for maximum interference removal and limited error propagation. The DFE may use a feed forward filter and a series connected chip-flow control buffer for receiving the input data signals. The DFE of the invention has application in 802.11 b PHY and 802.11 g PHY scenarios and any application involving a DFE with the need for minimum error propagation. Taught herein is a combined weighted DFE with erasure provision and interference removal in an optional two step mechanism. An article comprising a computer storage medium to execute the DFE design method is also disclosed.
1. A method of designing a decision feedback equalizer (DFE) for handling packet based complementary code keyed (CCK) symbols comprising chips, the method comprising the steps:
providing an inter symbol interference (ISI) loop for addressing removal of ISI caused between said CCK symbols, using symbol decisions;
providing an inter chip interference (ICI) loop for addressing removal of ICI caused between said chips of said CCK symbols in said ICI loop, using chip decisions; and,
placing said ICI loop to be nested within said ISI loop such that said packet based CCK symbols first enter the ISI loop.
2. The method as in claim 1 , including the step of implementing post-cursor interference removal using a feedback loop.
3. The method as in claim 1 , including the step of removing selected ones of said decisions that are prone to errors according to a threshold, by erasure.
4. The method as in claim 3 , including the step of scaling non-erased decisions by a weighting function, based on error probability.
5. The method as in claim 4 , wherein said weighting function and erasure threshold are controlled based on a technique using Euclidean distance.
6. The method as in claim 4 , wherein said weighting function and erasure threshold are controlled based on a minimum distance of in-phase (I) and quadrature (Q) paths.
7. The method as in claim 4 , wherein said weighting function and erasure threshold are controlled based on an average distance from an ideal constellation of in-phase and quadrature paths.
8. The method as in claim 2 , including the step of using a CCK modulator in the ISI loop.
9. The method as in claim 4 , including keeping said weighting function at a constant level.
10. The method as in claim 4 , including the step of computing said erasure threshold and weighting function based on said CCK symbols.
11. The method as in claim 1 , including the step of analyzing a decision error probability in said ICI loop.
12. The method as in claim 1 , including the step of measuring an error probability and using the measured error probability to optimize performance of said ISI and said ICI loops.
13. The method as in claim 12 , including the step of using a feed forward filter for receiving said packet based CCK symbols.
14. The method as in claim 13 , including the step of using an input buffer disposed in series with said feed forward filter, an output from said input buffer being connected to an input of said ISI loop.
15. A decision feedback equalizer (DFE) for use in a wireless local area network (WLAN) implementation, where packet based complementary code keying (CCK) symbols comprising chips are used, said DFE comprising:
an inter chip interference (ICI) loop for removal of interference caused between chips of said CCK symbols in said ICI loop, using chip decisions; and,
an inter symbol interference (ISI) loop for addressing interference caused between said CCK symbols, using symbol decisions;
said ICI loop being disposed within said ISI loop such that said packet based CCK symbols first enter the ISI loop.
16. The DFE as in claim 15 , wherein said ISI loop comprises a CCK modulator connected in series with a feedback filter.
17. The DFE as in claim 15 , including a CCK demodulator providing an output from the DFE, said CCK demodulator comprising a Fast Walsh Transform (FWT) unit connected in series with a maxima picker.
18. The DFE as in claim 15 , wherein said ICI loop includes a chip decision unit and a series connected weighted feedback filter.
19. The DFE as in claim 15 , including: a feed forward filter connected for receiving said packet based CCK symbols, an input buffer disposed in series with said feed forward filter, an output from said input buffer being connected to an input of said ISI loop, wherein said ISI loop includes a CCK modulator and a series connected feedback filter.
20. An article comprising a storage medium having instructions thereon which when executed by a computing platform result in execution of a method of designing a decision feedback equalizer (DFE) for handling packet based complementary code keyed (CCK) symbols comprising chips, the method comprising the steps of:
providing an inter chip interference (ICI) loop for addressing interference between said chips of said CCK symbols in said ICI loop, using chip decisions;
providing an inter symbol interference (ISI) loop for addressing interference between said CCK symbols, using symbol decisions; and,
placing said ICI loop to be nested within said ISI loop such that said packet based CCK symbols first enter the ISI loop.
21. The article as in claim 20 , including the step of implementing post-cursor interference removal using a feedback loop.
22. The article as in claim 20 , wherein the method includes the step of removing selected ones of said decisions that are prone to errors according to a threshold, by erasure.
23. The article as in claim 22 , wherein the method includes the step of scaling non-erased decisions by a weighting function, based on error probability.
24. The article as in claim 23 , wherein the method includes the step of computing said erasure threshold and weighting function based on said CCK symbols.