Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device and a method for fabricating the same is disclosed, in which a corner of a floating gate is rounded to reduce, minimize or prevent discharge of programmed electrons, and an overlap between the floating gate and a control gate increases to improve a coupling ratio and enable nonvolatile memory device operations at a low voltage. The nonvolatile memory device includes a device isolation layer in a field region on a semiconductor substrate, the device isolation having a trench; a tunnel oxide layer; a floating gate comprising a polysilicon pattern in an active region of the semiconductor substrate and a polysilicon spacer at the side of the polysilicon pattern and the inner sidewall of the trench; a gate dielectric layer on the floating gate; and a control gate on the gate dielectric layer overlapping with the floating gate.
1 . A nonvolatile memory device comprising:
a device isolation layer in a field region on a semiconductor substrate, the device isolation having a trench;
a tunnel oxide layer;
a floating gate comprising a polysilicon pattern in an active region of the semiconductor substrate and a polysilicon spacer at a side of the polysilicon pattern and an inner sidewall of the trench in the device isolation layer;
a gate dielectric layer on the floating gate; and
a control gate on the gate dielectric layer overlapping with the floating gate.
2 . The nonvolatile memory device of claim 1 , further comprising source and drain regions at sides of the control gate in the active region of the semiconductor substrate.
3 . The nonvolatile memory device of claim 1 , wherein the gate dielectric layer comprises an ONO layer.
4 . The nonvolatile memory device of claim 1 , wherein the control gate comprises polysilicon.
5 . The nonvolatile memory device of claim 1 , wherein the trench has a width substantially equal to or less than a width of the device isolation layer minus two times a width of a portion of the polysilicon pattern overlapping with the device isolation layer.
6 . A method for fabricating a nonvolatile memory device comprising:
forming a device isolation layer in a field region of a semiconductor substrate;
forming a tunnel oxide layer and a first polysilicon layer on the semiconductor substrate;
patterning the first polysilicon layer and the tunnel oxide layer;
forming a trench in the device isolation layer;
forming a polysilicon spacer at sides of the patterned first polysilicon layer and an inner sidewall of the trench; and
forming a gate dielectric layer and a control gate on the patterned first polysilicon layer and the polysilicon spacer.
7 . The method of claim 6 , wherein the step of forming the device isolation layer includes:
forming a buffer layer on the semiconductor substrate;
selectively removing the buffer layer from the field region;
etching the field region of the semiconductor substrate to the predetermined depth to form the trench; and
forming an insulating layer in the trench.
8 . The method of claim 6 , wherein the step of forming the polysilicon spacer includes:
forming a second polysilicon layer on the semiconductor substrate and the patterned first polysilicon layer; and
etching back the second polysilicon layer to leave the polysilicon spacer at the side of the patterned first polysilicon layer and at the inner sidewall of the trench in the device isolation layer.
9 . The method of claim 6 , further comprising forming source and drain regions by implanting impurity ions into the active region of the semiconductor substrate using the control gate as a mask.
10 . The method of claim 6 , wherein patterning the first polysilicon layer and the tunnel oxide layer comprises selectively removing portions of the tunneling oxide layer and the first polysilicon layer
11 . The method of claim 6 , wherein forming the trench comprises etching the device isolation layer to a predetermined depth.
12 . The method of claim 6 , comprising simultaneously forming the trench and patterning the tunnel oxide layer.
13 . The method of claim 6 , wherein the gate dielectric layer comprises an ONO layer.
14 . The method of claim 6 , wherein the control gate comprises polysilicon.
15 . The method of claim 6 , wherein the trench has a width substantially equal to or less than a width of the device isolation layer minus two times a width of a portion of the patterned first polysilicon layer that overlaps with the device isolation layer.