Dynamic random access memory cell and method for fabricating the same
View Patent ↗A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.
1. A method for fabricating a trench capacitor, comprising:
forming a trench in a substrate;
forming a first capacitor dielectric layer on a surface of said trench;
forming a conducting layer inside said trench;
after forming the conducting layer, directly forming a second capacitor dielectric layer on a surface of said substrate and on said conducting layer, wherein said substrate around said first and second capacitor dielectric layers serves as a bottom electrode, and said second capacitor dielectric layer is a silicon oxide/silicon nitride/silicon oxide (ONO) tacked layer or a silicon nitride/silicon oxide (NO) stacked layer;
forming a protruding electrode on said substrate, said protruding electrode being on said substrate around said trench, covering a junction between said trench and said substrate, and exposing a portion of said conducting layer; and
electrically connecting said protruding electrode and said conducting layer, said conducting layer and said protruding electrode being an upper electrode.
2. The trench capacitor of claim 1 , wherein said step of electrically connecting said protruding electrode and said conducting layer further comprises:
forming an inner dielectric layer on said substrate to cover said protruding electrode;
forming a contact window opening in said inner dielectric layer to expose a portion of said protruding electrode and said conducting layer; and
forming a conducting structure in said contact window opening.
3. A method for fabricating a dynamic random access memory cell, comprising:
forming a trench in a substrate;
forming a first capacitor dielectric layer on the surface of said trench;
forming a conducting layer inside said trench;
after forming the conducting layer, directly forming a second capacitor dielectric layer on the surface of said substrate and on said conducting layer, wherein said substrate around said first and second capacitor dielectric layers serves as a bottom electrode, and said second capacitor dielectric layer is a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer or a silicon nitride/silicon oxide (NO) stacked layer;
forming a protruding electrode and a gate electrode on said substrate, said protruding electrode being on said substrate around said trench, covering a junction between said trench and said substrate, and exposing a portion of said conducting layer;
forming a plurality of drain/source regions in said substrate beside two sides of said gate electrode; and
electrically connecting said protruding electrode and said conducting layer, and said conducting layer and said protruding electrode being an upper electrode.
4. The method of claim 3 , wherein said step of electrically connecting said protruding electrode and said conducting layer further comprises:
forming an inner dielectric layer on said substrate to cover said protruding electrode;
forming a contact window opening in said inner dielectric layer to expose a portion of said protruding electrode and said conducting layer; and
forming a conducting structure in said contact window opening.
5. The method of claim 3 , wherein after said step of forming said protruding electrode and said gate electrode, the method further comprises forming a plurality of spacers on sidewalls of said protruding electrode and said gate electrode.
6. The method of claim 3 , wherein after said step of forming said plurality of drain/source regions, the method further comprises forming a self-aligned silicide on an exposed portion of said protruding electrode and said conducting layer.
7. A method for fabricating a trench capacitor, comprising:
forming a trench in a substrate;
forming a first capacitor dielectric layer on a surface of said trench;
forming a conducting layer inside said trench;
after forming the conducting layer, directly forming a second capacitor dielectric layer on a surface of said substrate and on said conducting layer, wherein said substrate around said first and second capacitor dielectric layers serves as a bottom electrode, and said second capacitor dielectric layer is a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer or a silicon nitride/silicon oxide (NO) stacked layer;
forming a protruding electrode on said substrate, said protruding electrode being on said substrate around said trench, and covering a junction between said trench and said substrate; and
electrically connecting said protruding electrode and said conducting layer, said conducting layer and said protruding electrode being an upper electrode, wherein said upper electrode is isolated from said substrate.
8. The trench capacitor of claim 7 , wherein said step of electrically connecting said protruding electrode and said conducting layer further comprises:
forming an inner dielectric layer on said substrate to cover said protruding electrode;
forming a contact window opening in said inner dielectric layer to expose a portion of said protruding electrode and said conducting layer; and
forming a conducting structure in said contact window opening.
9. A method for fabricating a dynamic random access memory cell, comprising:
forming a trench in a substrate;
forming a first capacitor dielectric layer on the surface of said trench;
forming a conducting layer inside said trench;
after forming the conducting layer, directly forming a second capacitor dielectric layer on the surface of said substrate and on said conducting layer, wherein said substrate around said first and second capacitor dielectric layers serves as a bottom electrode, and said second capacitor dielectric layer is a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer or a silicon nitride/silicon oxide (NO) stacked layer;
forming a protruding electrode and a gate electrode on said substrate, said protruding electrode being on said substrate around said trench, and covering a junction between said trench and said substrate;
forming a plurality of drain/source regions in said substrate beside two sides of said gate electrode; and
electrically connecting said protruding electrode and said conducting layer, and said conducting layer and said protruding electrode being an upper electrode, wherein said upper electrode is isolated from said substrate.
10. The method of claim 9 , wherein said step of electrically connecting said protruding electrode and said conducting layer further comprises:
forming an inner dielectric layer on said substrate to cover said protruding electrode;
forming a contact window opening in said inner dielectric layer to expose a portion of said protruding electrode and said conducting layer; and
forming a conducting structure in said contact window opening.
11. The method of claim 9 , wherein after said step of forming said protruding electrode and said gate electrode, the method further comprises forming a plurality of spacers on sidewalls of said protruding electrode and said gate electrode.
12. The method of claim 9 , wherein after said step of forming said plurality of drain/source regions, the method further comprises forming a self-aligned suicide on an exposed portion of said protruding electrode and said conducting layer.