Highly compact non-volatile memory and method therefor with internal serial buses
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.
1. A non-volatile memory device, comprising:
an array of memory cells;
a set of read/write circuits for operating on a set of memory cells in parallel among said array;
said set of read/write circuits having a plurality of components forming one or more component groups;
a bus servicing each component group; and
a bus controller coupled to components among each component group to control bus operations therein.
2. A non-volatile memory device as in claim 1 , wherein:
data is exchanged between components among each component group; and
said bus transfers the data serially.
3. A non-volatile memory device as in claim 1 , wherein:
said bus controller couples to components among each component group via a set of control lines.
4. A non-volatile memory device as in claim 1 , wherein:
said bus is further segmented into a first and second segments;
said first segment is coupled to a first group of components among each component group;
said second segment is coupled to a second group of components among each component group; and
at least one of the components is common to said first and second groups.
5. A non-volatile memory device, comprising:
an array of memory cells;
a set of read/write circuits for operating on a set of memory cells in parallel among said array;
said set of read/write circuits having a plurality of components forming one or more component groups;
a bus servicing each component group; and
means for controlling operations of components among each component group with its bus.
6. A non-volatile memory device as in claim 5 , wherein:
data is exchanged between components among each component group; and
said bus transfers the data serially.
7. A non-volatile memory device as in claim 5 , wherein:
said means for controlling further comprising:
a set of control lines coupled to components among each component group for sending control signals thereto.
8. A non-volatile memory device as in claim 5 , wherein:
said bus is further segmented into a first and second segments;
said first segment is coupled to a first group of components among each component group;
said second segment is coupled to a second group of components among each component group; and
at least one of the components is common to said first and second groups.
9. A non-volatile memory device as in any one of claims 1 – 8 , wherein said array of memory cells is constituted from flash EEPROM cells.
10. A non-volatile memory device as in any one of claims 1 – 8 , wherein said array of memory cells is constituted from NROM cells.
11. A non-volatile memory device as in any one of claims 1 – 8 , wherein each memory cell stores one bit of data.
12. A non-volatile memory device as in any one of claims 1 – 8 , wherein each memory cell stores more than one bit of data.
13. A method of reducing the number of connections between a set of read/write circuits in a non-volatile memory, comprising:
partitioning the set of read/write circuits into components;
organizing the components of the set of read/write circuits into one or more component groups;
coupling the components of each component group by a bus; and
controlling operations of the components of each component group and its bus by sending control signals thereto.
14. A method of reducing the number of connections between a set of read/write circuits in a non-volatile memory as in claim 13 , further including:
exchanging data between components among each component group; and
transferring data serially between components among each component group by the bus.
15. A method of reducing the number of connections between a set of read/write circuits in a non-volatile memory as in claim 13 , further including: sending the control signals simultaneously to similar individual component groups.
16. A method of reducing the number of connections between a set of readlwrite circuits in a non-volatile memory as in claim 13 , further including:
segmenting said bus into first and second segments;
coupling said first segment to a first group of components among each component group; and
coupling said second segment to a second group of components among each component group,
wherein at least one of the components is common to said first and second groups.
17. A method as in any one of claims 13 – 16 , wherein said array of memory cells is constituted from flash EEPROM cells.
18. A method as in any one of claims 13 – 16 , wherein said array of memory cells is constituted from NROM cells.
19. A method as in any one of claims 13 – 16 , wherein each memory cell stores one bit of data.
20. A method as in any one of claims 13 – 16 , wherein each memory cell stores more than one bit of data.