System and method for characterizing a signal path using a sub-chip sampler

1. A system for characterizing a signal path, comprising:

a system clock configured to produce a system clock signal at a sample frequency;

a frequency divider configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency;

a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal; and

a sub-chip sampler configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency.

2. A system as in claim 1 , wherein the PN sequence generator is configured to be programmable to enable the PN sequence generator to produce two or more types of PN sequences.

3. A system as in claim 2 , wherein the PN sequence generator is configured to be programmed to produce a maximal length PN code.

4. A system as in claim 2 , wherein a seed logic is fed to an initial state of the PN sequence generator.

5. A system as in claim 1 , wherein the sub-chip sampler further comprises a shift register configured to shift the PN-sequence by one sub-chip each cycle of the system clock signal.

6. A system as in claim 5 , wherein the shift register is comprised of a plurality of D type flip-flops.

7. A system as in claim 1 , wherein the sub-chip sampler further comprises a surface acoustic wave structure configured to delay the PN-sequence by one or more sub-chip cycles.

8. A system as in claim 1 , wherein the sub-chip sampler further comprises a means for multiplying the reflected PN sequence with the PN sequence.

9. A system as in claim 8 , wherein the means for multiplying is a radio frequency mixer.

10. A system as in claim 9 , wherein the mixer is a doubly balanced Gilbert mixer.

11. A system as in claim 9 , wherein the sub-chip sampler further comprises an operational amplifier (op-amp) configured to receive a differential output of the mixer and convert it to a single ended signal.

12. A system as in claim 11 , wherein the sub-chip sampler further comprises a means for integrating the single ended signal to output a correlated signal.

13. A system as in claim 12 , wherein the sub-chip sampler further comprises a peak detector configured to receive the correlated signal and detect a peak in the signal, wherein the peak signifies a discontinuity in the signal path.

14. A system as in claim 12 , further comprising a plurality of correlation sections comprising the mixer, the operational amplifier, and the integration means.

15. A system as in claim 1 , wherein the PN sequence is modulated by a carrier signal to generate a binary phase shift keying (BPSK) signal to be coupled to the signal path while the signal path is carrying an operational signal.

16. A system as in claim 1 , wherein the PN sequence generator is configured to generate the PN-sequence at a power level below a noise floor of the signal path.

17. A system as in claim 1 , wherein the system clock is configured to operate at a frequency of approximately 1 GHz.

18. A system as in claim 1 , wherein the chip clock is configured to operate at a frequency of approximately 125 MHz.

19. A system as in claim 1 , wherein the sub-chip sampler further comprises a delay located before the sub-chip sampler and configured to delay a PN-code sequence by a predetermined amount of time to enable the system to characterize a desired portion of the signal path.

20. A system for characterizing a signal path, comprising

a system clock configured to produce a system clock signal at a sample frequency;

a frequency divider configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency;

a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal;

a sub-chip sampler configured to correlate the PN sequence with a reflected PN sequence, which has been reflected within the signal path, to produce a correlated signal and sample the correlated signal at the sample frequency, wherein the sub-chip sampler further comprises:

a shift register configured to shift the PN sequence relative to the reflected PN sequence by one sub-chip each cycle of the system clock;

a means for multiplying the reflected PN sequence with the PN sequence to produce the correlated signal; and

a means for integrating the correlated signal.

21. A system as in claim 20 , wherein the means for multiplying the reflected PN sequence with the PN sequence comprises a radio frequency mixer.

22. A system as in claim 20 , wherein the means for integrating correlated signal comprises an RC integrator.

23. A system as in claim 20 , further comprising a peak detector configured to locate a peak within the correlated signal, wherein the peak signifies a discontinuity in the signal path.

24. A method for characterizing a signal path, comprising the steps of:

generating a system clock signal at a sample frequency;

dividing the system clock frequency by N to produce a chip clock signal at a chip frequency, wherein the chip frequency is a factor of 1/N of the sample frequency;

producing a pseudo-noise (PN) sequence at the chip frequency;

coupling the pseudo-noise sequence to the signal path while the signal path is carrying an operational signal;

correlating the pseudo-noise sequence with a reflected PN sequence which has been reflected within the signal path to form a correlated signal; and

sampling the correlated signal at the sample frequency.