Method and system for memory access
View Patent ↗Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.
1. A method for memory access, said method comprising:
accessing a first block of data from a first memory chip, wherein the first block of data comprises one word from each memory bank in the first memory chip;
accessing a second block of data from a second memory chip, wherein the second block of data comprises one word from each memory bank in the second memory chip;
determining if the first block of data and the second block of data are sequential;
if the first block of data and the second block of data are sequential, appending the second block of data to the first block of data; and
if the first block of data and the second block of data are not sequential,
storing the second block of data in a buffer;
accessing a third block of data from the first memory chip;
appending the third block of data to the first block of data; and
appending the second block of data to the third block of data.
2. The method of claim 1 , wherein the words in the memory banks are 16 bits.
3. The method of claim 1 , wherein the words in the memory banks are 32 bits.
4. The method of claim 1 , wherein the words in the memory banks are 48 bits.
5. The method of claim 1 , wherein the words in the memory banks are 64 bits.
6. The method of claim 1 , wherein the first memory chip and the second memory chip each comprise four memory banks.
7. The method of claim 1 , wherein the method further comprises commanding the first memory chip and the second memory chip to be accessed on alternating cycles.
8. The method of claim 1 , wherein the first memory chip is accessed prior to the second memory chip for a first period of time, and wherein the first memory chip is accessed after the second memory chip for a second period of time.
9. A system for memory access, said method comprising:
a first memory chip having a first plurality of memory banks, wherein one word in a first block of data is stored in each memory bank in the first plurality of memory banks;
a second memory chip having a second plurality of memory banks, wherein one word in a second block of data is stored in each memory bank in the first plurality of memory banks;
a first circuit for accessing the first block of data and the second block of data;
a first buffer for receiving the first block of data and the second block of data if the first block of data and the second block of data are sequential; and
a second buffer for storing the second block of data, while the first circuit accesses a third block of data from the first memory chip, if the first block of data and the second block of data are not sequential.
10. The system of claim 9 , wherein the words in the memory banks are 16 bits.
11. The system of claim 9 , wherein the words in the memory banks are 32 bits.
12. The system of claim 9 , wherein the words in the memory banks are 48 bits.
13. The system of claim 9 , wherein the words in the memory banks are 64 bits.
14. The system of claim 9 , wherein the first memory chip and the second memory chip each comprise four memory banks.
15. The system of claim 9 , wherein the system further comprises a command bus for commanding the first memory chip and the second memory chip to be accessed on alternating cycles.
16. The system of claim 15 , wherein the command bus commands the first memory chip to be accessed prior to the second memory chip for a first period of time, and wherein the command bus further commands the first memory chip to be accessed after the second memory chip for a second period of time.