Semiconductor device and programming method
View Patent ↗The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
1. A semiconductor device comprising:
a core cell array having memory cells;
a reference cell array having reference cells used to identify data in the memory cells; and
a dummy cell array including a programmable dummy cell that is located proximately to the reference cell array, wherein the dummy cell array is connected to a word line to which the core cell array and the reference cell array are connected and is located between the core cell array and the reference cell array.
2. The semiconductor device as claimed in claim 1 , wherein:
the dummy cell array comprises another programmable dummy cell that is located proximately to the core cell array.
3. The semiconductor device as claimed in claim 1 , wherein the core cell array, the reference cell array and the dummy cell array are of a virtual ground type in which neighboring cells share a bit line.
4. The semiconductor device as claimed in claim 1 , wherein:
the core cell array, the reference cell array and the dummy cell array are of a virtual ground type in which neighboring cells share a bit line, and each of the neighboring cells is capable of storing two bits of data; and
one of the two bits of the programmable dummy cell closer to the reference cell array has a programmed state.
5. The semiconductor device as claimed in claim 1 , further comprising a decoder generating a decode signal commonly applied to the core cell array, the reference cell array and the dummy cell array.
6. A semiconductor device comprising:
a core cell array having memory cells:
a reference cell array having reference cells used to identify data in the memory cells; and
a dummy cell array including a programmable dummy cell that is located proximately to the reference cell array, further comprising a control circuit that programs the reference cells so that programming of the reference cells starts from both edges of the reference cell array and progresses towards the center thereof.
7. The semiconductor device as claimed in claim 1 , further comprising a control circuit that programs the programmable dummy cell located at an edge of the dummy cell array after erasing data in the core cell array and the reference cell array, and then programs the reference cell array.
8. The semiconductor device as claimed in claim 1 , wherein the memory cells have a charge trap layer made of an insulator, and bits of data are stored in the charge trap layer.
9. The semiconductor device as claimed in claim 1 , wherein the programmable dummy cell located proximately to the reference cell array has a programmed state.
10. The semiconductor device as claimed in claim 1 , wherein the dummy cell array comprises another programmable dummy cell, and the reference cell array is sandwiched between the programmable dummy cell and said another programmable dummy cell.
11. The semiconductor device as claimed in claim 1 , wherein the dummy cell array comprises multiple programmable dummy cells, and only programmable dummy cell or cells among the multiple programmable dummy cells located proximately to the reference cell array have a programmed state.
12. The semiconductor device as claimed in claim 1 , wherein the programmable dummy cell is located next to the reference cell array.
13. A method of programming a reference cell array having reference cells used to identify data in memory cells, comprising the steps of:
erasing data in the memory cells and the reference cells of the reference cell array;
programming a dummy cell of a dummy cell array located proximately to the reference cell array; and
programming the reference cell array after the step of programming the dummy cell, wherein the step of programming of the reference cell array starts from reference cells located at both edges of the reference cell array.