Semiconductor memory device and control method having data protection feature
View Patent ↗A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
1. A semiconductor device comprising:
a first memory cell array that includes memory cells for storing data and is managed on a sector basis;
a second memory cell array including memory cells storing sector protection information on the sector basis; and
a control circuit checking the sector protection information stored in the second memory cell array when a sector is to be modified, wherein the control circuit delays the timing of polling when reading the sector protection information from the second memory cell array.
2. The semiconductor device as claimed in claim 1 , wherein the control circuit performs erasing on the basis of the sector protection information read from the second memory cell array.
3. The semiconductor device as claimed in claim 1 , further comprising an output terminal, wherein a route from the second memory cell array to the output terminal has a portion shared by a route from the first memory cell array to the output terminal.
4. The semiconductor device as claimed in claim 1 , wherein the memory cells of the second memory cell array are assigned to a domain corresponding to a terminal via which the sector protection information is output to an outside of the semiconductor device.
5. The semiconductor device as claimed in claim 1 , wherein the second memory cell array is disposed on an extension of a sector array of the first memory cell array.
6. The semiconductor device as claimed in claim 5 , further comprising signal lines for selecting memory cells in the first memory cell array, and the signal lines include a signal line used to select one of the memory cells in the second memory cell array.
7. The semiconductor device as claimed in claim 5 , further comprising means for selecting memory cells in the first memory cell array, wherein the means for selecting includes a circuit used to select one of the memory cells in the second memory cell array.
8. The semiconductor device as claimed in claim 1 , further comprising a write circuit that writes data into the memory cells of the second memory cell array.
9. The semiconductor device as claimed in claim 1 , wherein a third memory cell array including one-time programmable memory cells.
10. The semiconductor device as claimed in claim 9 , wherein the third memory cell array is disposed on an extension of a sector array of the first memory cell array.
11. The semiconductor device as claimed in claim 10 , wherein the third memory cell array is provided on a sector array different from that of the second memory cell array.
12. The semiconductor device as claimed in claim 9 , further comprising signal lines for selecting memory cells of the first memory cell array, wherein the signal lines include a signal line used to select one of the one-time programmable memory cells of the third memory cell array.
13. The semiconductor device as claimed in claim 9 , comprising means for selecting memory cells in the first memory cell array, wherein the means for selecting includes a circuit used to select one of the one-time programmable memory cells in the third memory cell array.
14. The semiconductor device as claimed in claim 1 , wherein the semiconductor device is a semiconductor memory device.
15. A semiconductor device comprising:
a first memory cell array that includes memory cells for storing data and is managed on a sector basis;
a second memory cell array including memory cells storing sector protection information on the sector basis; and
a control circuit checking the sector protection information stored in the second memory cell array when a sector is to be modified, wherein a third memory cell array includes one-time programmable memory cells, further comprising global word lines shared by selection of the memory cells in the second memory cell array and selection of one of the one-time programmable memory cells in the third memory cell array.
16. A semiconductor device comprising:
a first memory cell array that includes memory cells for storing data and is managed on a sector basis;
a second memory cell array including memory cells storing sector protection information on the sector basis; and
a control circuit checking the sector protection information stored in the second memory cell array when a sector is to be modified, further comprising:
a volatile memory circuit storing another sector protection information on the sector basis; and
a circuit part selectively outputting the sector protection information in the second memory cell array and said another sector protection information in the volatile memory circuit.
17. The semiconductor device as claimed in claim 16 , wherein the circuit part selects said another sector protection information in the volatile memory circuit when said another sector protection information shows protection of data in the first memory cell array.
18. The semiconductor device as claimed in claim 17 , wherein the circuit part selects the sector protection information in the second memory cell array when said another sector protection information in the volatile memory circuit shows unprotection of data in the first memory cell array.
19. The semiconductor device as claimed in claim 16 , wherein the circuit part comprises an output inversion circuit that inverts the sector protection information selected.
20. A semiconductor device comprising:
a first memory cell array that includes memory cells for storing data and is managed on a sector basis;
a second memory cell array including memory cells storing sector protection information on the sector basis; and
a control circuit checking the sector protection information stored in the second memory cell array when a sector is to be modified, further comprising an X decoder for the first memory cell array and an X decoder for the second memory cell array, wherein the X decoder for the second memory cell array is configured so as to have a multiple of a minimum unit of the X decoder for the first memory cell array.
21. The semiconductor device as claimed in claim 20 , further comprising an address control circuit producing different addresses in a user mode and a test mode so that a domain of the memory cells of the second memory cell array can be changed.
22. The semiconductor device as claimed in claim 21 , wherein the address control circuit selects, in the user mode, one of the memory cells of the second memory cell array using an address for selecting one of the sectors of the first memory cell array.
23. The semiconductor device as claimed in claim 21 , wherein the address control circuit selects, in the test mode, one of the memory cells of the second memory cell array using an address for selecting one of the sectors of the first memory cell array.
24. The semiconductor device as claimed in claim 21 , further comprising a control circuit that provides the address control circuit with a control signal for switching the address used in the address control circuit after receiving a given user command.
25. The semiconductor device as claimed in claim 21 , further comprising a control circuit that provides the address control circuit with a control signal for switching the address used in the address control circuit after receiving a given test command.