Semiconductor device and control method of the same
View Patent ↗The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
1. A semiconductor device comprising:
a memory storing information that determines an activated state;
a latch circuit that latches activation information based on the information stored in the memory;
an activation control circuit causing the latch circuit to latch the activation information by referring to the memory when a given command is input after activation, wherein, when the memory is in an erased state, the activation control circuit produces a reset signal that resets the latch circuit.
2. The semiconductor device as claimed in claim 1 , wherein the activation control circuit causes the latch circuit to latch the activation information when the given command is first input.
3. The semiconductor device as claimed in claim 1 , wherein, when the memory is in a programmed state, the activation control circuit produces a given set signal that causes the activation information to be written into the latch circuit.
4. The semiconductor device as claimed in claim 1 , further comprising a memory cell array that includes memory cells for storing data and is managed on a sector basis, wherein the latch circuit latches the activation information on the sector basis.
5. The semiconductor device as claimed in claim 4 , wherein the latch circuit latches a single piece of the activation information for multiple sectors.
6. The semiconductor device as claimed in claim 4 , wherein the given command is a write command.
7. The semiconductor device as claimed in claim 4 , wherein the information that is stored in the memory and determines the activated state includes information indicating whether each sector should be activated in a protected state or in an unprotected state.
8. The semiconductor device as claimed in claim 4 , wherein the memory is a content addressable memory.
9. The semiconductor device as claimed in claim 4 , further comprising an erase circuit that erases data in the memory cells in the memory cell array on the basis of the activation information latched in the latch circuit.
10. The semiconductor device as claimed in claim 9 , further comprising a control circuit that controls erasing by the erase circuit on the basis of the activation information latched in the latch circuit.
11. The semiconductor device as claimed in claim 4 , wherein the latch circuit comprises:
first circuits that latch the activation information on the sector basis; and
a second circuit that is commonly provided to the first circuits and decodes an address.
12. The semiconductor device as claimed in claim 11 , wherein the latch circuit further comprises a third circuit that is commonly provided to the first circuits and outputs the activation information latched in the first circuits.
13. A semiconductor device comprising:
a memory storing information that determines an activated state;
a latch circuit that latches activation information based on the information stored in the memory;
an activation control circuit causing the latch circuit to latch the activation information by referring to the memory when a given command is input after activation;
wherein, in a case where the activation control circuit causes the activation control circuit to latch the activation information when a power supply voltage is equal to or lower than a predetermined voltage, the activation control circuit causes the activation control circuit to latch the given command again when the given command is input again.
14. A semiconductor device comprising:
a memory storing information that determines an activated state;
a latch circuit that latches activation information based on the information stored in the memory;
an activation control circuit causing the latch circuit to latch the activation information by referring to the memory when a given command is input after activation;
wherein, in a case where the activation control circuit causes the activation control circuit to latch the activation information when a power supply voltage is higher than a given power supply voltage, the activation control circuit does not cause the activation control circuit to latch the given command even when the given command is input again.
15. A semiconductor device comprising:
a memory storing information that determines an activated state;
a latch circuit that latches activation information based on the information stored in the memory;
an activation control circuit causing the latch circuit to latch the activation information by referring to the memory when a given command is input after activation;
further comprising a memory cell array that includes memory cells for storing data and is managed on a sector basis, wherein the latch circuit latches the activation information on the sector basis;
further comprising a second memory cell array having memory cells for storing sector protection information, wherein the control circuit determines whether the memory cell array should be erased on the basis of the activation information latched in the latch circuit and the sector protection information stored in the second memory cell array.
16. A semiconductor device comprising:
a memory cell array that includes memory cells for storing data and is managed on a sector basis;
a latch circuit including first circuits each latching information on a respective sector of the memory cell array, and a second circuit that is commonly provided to the first circuits and decodes an address; and
a control circuit controlling sectors of the memory cell array on the basis of the information latched in the first circuits.
17. The semiconductor device as claimed in claim 16 , wherein the latch circuit further comprises a third circuit that is commonly provided to the first circuits and outputs the information latched in the first circuits.
18. The semiconductor device as claimed in claim 17 , wherein the third circuit is commonly provided to the first circuits respectively corresponding to sectors in a given block.
19. The semiconductor device as claimed in claim 16 , wherein the second circuit is commonly provided to the first circuits respectively corresponding to sectors in a given block.
20. The semiconductor device as claimed in claim 16 , wherein the information on the respective sector is sector protection information.
21. The semiconductor device as claimed in claim 16 , wherein the information on the respective sector is erase information.
22. The semiconductor device as claimed in claim 16 , wherein the control circuit controls programming or erasing of a sector in the memory cell array on the basis of the information latched in the latch circuit.
23. A semiconductor device comprising:
a memory cell array that includes memory cells for storing data and is managed on a sector basis;
a latch circuit including first circuits each latching information on a respective sector of the memory cell array, and an additional circuit that is commonly provided to the first circuits and outputs the information latched in the first circuits; and
a control circuit controlling sectors of the memory cell array on the basis of the information latched in the first circuits.