Semiconductor integrated circuit and fabrication process thereof
View Patent ↗A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in the second device region.
1. A method of fabricating a semiconductor integrated circuit device, said semiconductor integrated circuit device comprising a silicon substrate defined with a first device region and a second device region by a device isolation structure, an n-channel MOS transistor formed on said first device region and having a first gate electrode pattern, and a p-channel MOS transistor formed on said second device region and having a second gate electrode pattern, said p-channel MOS transistor including p-type SiGe mixed crystal regions formed epitaxially to said silicon substrate at both lateral sides of a channel region right underneath said second gate electrode pattern, said method comprising the steps of:
forming, in each of said first and second device regions, a first sidewall insulation film on respective sidewall surfaces of said first gate electrode pattern and said second gate electrode pattern by using a first material having resistance against HF;
forming a source region and a drain region of p-type in said silicon substrate at both lateral sides of said second gate electrode pattern by conducting an ion implantation process of a p-type impurity element in said second device region while using said second electrode pattern and said fist sidewall insulation film on said second gate electrode pattern as a self-aligned mask;
forming, in said first device region, a second sidewall insulation film having an etching selectivity to said first sidewall insulation film, on said first sidewall insulation film formed on said first gate electrode pattern;
forming a source region and a drain region of n-type in said first device region at both lateral sides of said first gate electrode pattern, by conducting an ion implantation process of an n-type impurity element in said first device region while using said first gate electrode pattern, said first sidewall insulation film and said second sidewall insulation film on said first gate electrode pattern as a self-aligned mask;
forming a mask insulation film so as to cover said first device region and expose said second device region;
forming, after said step of forming said mask insulation film, first and second trenches at both lateral sides of said second gate electrode pattern with separation therefrom by said first sidewall insulation film, by etching said silicon substrate in said second device region while using said second gate electrode pattern and said first sidewall insulation film on said second gate electrode pattern as a mask; and
forming, after said step of forming said first and second trenches, said p-type SiGe mixed crystal regions by causing an epitaxial growth of a p-type SiGe mixed crystal layer in said first and second trenches in a state in which said first device region is covered with said mask insulation film.
2. The method as claimed in claim 1 , wherein said step of etching said silicon substrate comprises any of the step of processing a surface of said first and second trenches with HF or an organic alkaline etchant and the step of processing said surface of said first and second trenches by a combination of an isotropic dry etching process or a wet etching process that uses HF or said organic alkaline etchant and a dry etching process.
3. The method as claimed in claim 1 , further comprising the steps of:
forming source and drain extension regions of n-type in said silicon substrate at both lateral sides of said first gate electrode in correspondence to an edge of said first gate electrode, by introducing, before said step of formation of said first sidewall insulation film, an n-type impurity element into said first device region while using said first gate electrode as a mask; and
forming source and drain extension regions of p-type in said silicon substrate at both lateral sides of said second gate electrode in correspondence to an edge of said second gate electrode, by introducing, before said step of forming said first sidewall insulation film, a p-type impurity element into said second device region while using said second gate electrode as a mask,
said formation step of said source and drain regions of n-type and said formation step of said source and drain regions of p-type are conducted concurrently.
4. The method as claimed in claim 1 , wherein said step of forming said first and second sidewall insulation films comprises the steps of:
forming, before formation of said first and second sidewall insulation films, an oxide film on a surface of said first and second gate electrodes such that said oxide film covers continuously said respective sidewall surfaces of said first and second gate electrodes and further respective surface parts of said silicon substrate on which said first and second gate electrodes are formed;
wet etching, after said step of forming said first and second sidewall insulation films, said oxide film in HF to form first and second slits in said first and second gate electrodes respectively, such that said first slit extends between said sidewall surface of said first gate electrode and said first sidewall insulation film and between said first sidewall insulation film and a part of said silicon substrate underneath said first sidewall insulation film, and such that said second slit extends between said sidewall surface of said second gate electrode and second first sidewall insulation film and between said second sidewall insulation film and a part of said silicon substrate underneath said second sidewall insulation film; and
filling said first and second slits with an insulation film resistant against HF.
5. The method as claimed in claim 1 , wherein said second sidewall insulation film on said first gate electrode pattern is formed, after formation of said p-type SiGe mixed crystal regions, by etching back an insulation film having an etching selectivity to said first sidewall insulation film and provided on said first sidewall insulation film.
6. The method as claimed in claim 5 , wherein said step of forming said source and drain regions of n-type in said first device region comprises the step of introducing said n-type impurity element by an ion implantation process under a first acceleration voltage with a first dose, said step of forming said source and drain regions of n-type further comprises the step, conducted concurrently to said step of forming said source and drain regions of p-type in said second device region, of introducing said second impurity element into said first device region by an ion implantation process with a second acceleration voltage larger than said first acceleration voltage with a second dose smaller than said first dose while using said first gate electrode pattern and said first sidewall insulation film on said first gate electrode pattern as a self-aligned mask.
7. The method as claimed in claim 1 , wherein said step of forming said second sidewall insulation film on said first sidewall insulation film on said first gate electrode pattern in said first device region further comprises the step of forming said second sidewall insulation film also on said first sidewall insulation film on said second gate electrode pattern, said step of forming said source and drain regions of p-type in said second device region is conducted after said step of forming said source and drain regions of n-type in said first device region in the state in which said second sidewall insulation film on said second gate electrode pattern is removed.
8. The method as claimed in claim 7 , wherein said step of forming said second insulation film in said first device region on said first sidewall insulation film on said first gate electrode pattern further comprises the step of concurrently forming said second sidewall insulation film on said first sidewall insulation film on said second gate electrode pattern in said second device region,
said step of forming said source and drain regions of p-type in said second device region is conducted prior to said step of forming said second sidewall insulation film on said second gate electrode pattern.
9. The method as claimed in claim 8 , wherein said step of forming said source and drain regions of p-type in said second device region comprises the steps of introducing said p-type impurity element by an ion implantation process under a first acceleration voltage with a first dose and introducing said p-type impurity element by an ion implantation process under a second, larger acceleration voltage with a second, smaller dose.