Radiation-hardened programmable device
View Patent ↗A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.
1. A radiation-hardened SRAM memory cell comprising:
complementary column select lines;
a row select line;
cross-coupled first and second P-channel transistors;
cross-coupled first and second N-channel transistors, the current paths of the first P-channel and first N-channel transistors being coupled together at a first node and the current paths of the second P-channel and second N-channel transistors being coupled together at a second node;
a pair of pass transistors for transferring a complementary data state from the first and second nodes to the complementary column select lines,
wherein a gate of the first N-channel transistor is biased to ground and the gate of the second N-channel transistor is biased to VDD, the first and second N-channel transistors being irradiated to a sufficient dosage to establish a permanent data state in the memory cell.
2. A radiation-hardened memory cell as in claim 1 in which each of the pair of pass transistors comprise N-channel transistors.
3. A radiation-hardened memory cell as in claim 1 in which the first and second N-channel transistors have been exposed to a total dose or radiation between 300K and 1 MEG RADs.
4. A radiation-hardened SRAM memory cell comprising:
first and second nodes;
first and second transistors having current paths coupled at the first node, and gates coupled to the second node;
third and fourth transistors having current paths connected at the second node, and gates coupled to the first node, wherein
the second and fourth transistors being irradiated with a sufficient dosage to induce a permanent complimentary data state at the first and second nodes.
5. The memory cell of claim 4 in which the second and fourth transistors each comprise N-channel transistors.
6. The memory cell of claim 4 in which the first and third transistors each comprise P-channel transistors.
7. The memory cell of claim 4 in which the gate of the second transistor is set to a logic one voltage and the gate of the fourth transistor is set to a logic zero voltage prior to irradiation.
8. The memory cell of claim 7 in which the logic one voltage is about 2.7 volts and the logic zero voltage is about zero volts.
9. The memory cell of claim 4 further comprising:
a pair of complementary column select lines;
means for coupling the complementary column select lines to the first and second nodes; and
a row select line coupled to the coupling means.
10. The memory cell of claim 9 in which the coupling means comprises first and second pass transistors.
11. The memory cell of claim 10 in which the first pass transistor comprises an N-channel transistor having a gate coupled to the row select line.
12. The memory cell of claim 10 in which the second pass transistor comprises an N-channel transistor having a gate coupled to the row select line.