Tunneling-enhanced floating gate semiconductor device
Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and a surface region on a substrate are implanted with the impurities based on a number of predetermined configurations. In another embodiment, a transistor type semiconductor device is configured with implanted impurities in two regions of its floating gate as well as two surface regions in its substrate. Enhanced tunneling junction enables use of lower tunneling voltages in applications such as programming NVM cells.
1 . A tunneling-enhanced floating gate device, comprising:
a substrate that includes impurities of p-type;
an n-well within the substrate that includes impurities of n-type;
a floating gate structure disposed over the n-well, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region; and
a first surface region in the n-well, wherein the first surface region is located about the third region of the floating gate structure.
2 . The device of claim 1 , wherein
the first region and the third region are doped with implants of at least one of a first type and a second type impurities; and
the first surface region is doped with implants of the first type impurities.
3 . The device of claim 1 , wherein
the first region is doped with implants of one of a first type and a second type impurities;
the third region is doped with implants of another of the first type and the second type impurities; and
the first surface region is doped with implants of the second type impurities.
4 . The device of claim 1 , wherein
the first region and the third region are doped with implants of a first type impurities; and
the first surface region is doped with implants of a second type impurities.
5 . The device of claim 4 , wherein
the first type impurities include p-type impurities; and
the second type impurities include n-type impurities.
6 . The device of claim 1 , further comprising:
a second surface region that is located about the first surface region away from the floating gate structure, wherein the second surface region is doped with implants of n-type impurities.
7 . The device of claim 6 , wherein
the first surface region and the second surface region are one of overlapping, abutting, and separated by another region.
8 . The device of claim 6 , further comprising:
a first contact region in the first surface region that is arranged to receive a tunneling voltage.
9 . The device of claim 6 , further comprising:
a second contact region in the second surface region that is also arranged to receive the tunneling voltage.
10 . The device of claim 1 , wherein
the floating gate structure is arranged such that the third region and the first surface region are one of overlapping, non-overlapping, and approximately adjacent thereto.
11 . The device of claim 1 , further comprising:
at least one of a first field oxide region and a second field oxide region that are arranged to define boundaries of the n-well.
12 . A method for creating a tunneling-enhanced floating gate device, comprising:
forming a substrate that includes impurities of p-type;
forming an n-well within the substrate that includes impurities of n-type;
forming a floating gate structure disposed over the n-well, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region;
forming a first surface region in the n-well, wherein the first surface region is located about the third region of the floating gate structure; and
forming a second surface region that is located about the first surface region away from the floating gate structure, wherein the second surface region is doped with implants of n-type impurities.
13 . The method of claim 12 , further comprising:
forming a first contact region in the first surface region that is arranged to receive a tunneling voltage;
forming a second contact region in the second surface region that is also arranged to receive the tunneling voltage; and
forming at least one field oxide region at one end of the n-well.
14 . The method of claim 12 , further comprising:
doping the first region and the third region with implants of at least one of a first type and a second type impurities; and
doping the first surface region with implants of the first type impurities.
15 . The method of claim 12 , further comprising:
doping the first region with implants of one of a first type and a second type impurities;
doping the third region with implants of another of the first type and the second type impurities; and
doping the first surface region with implants of the second type impurities.
16 . The method of claim 12 , further comprising:
doping the first region and the third region with implants of one of a first type and a second type impurities; and
doping the first surface region with implants of the second type impurities.
17 . The method of claim 16 , wherein
the first type impurities include p-type impurities; and
the second type impurities include n-type impurities.
18 . A tunneling-enhanced floating gate device, comprising:
a substrate that includes impurities of p-type;
an n-well within the substrate that includes impurities of n-type;
a first surface region in the n-well;
a second surface region in the n-well;
a floating gate structure disposed over a region in the n-well defined by the first surface region and the second surface region, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region; and
a third surface region that is located about the second surface region away from the floating gate structure, wherein the third surface region is doped with implants of n-type impurities.
19 . The device of claim 18 , wherein
the first surface region and the second surface region are doped with implants of at least one of a first type and a second type impurities; and
the first region is doped with implants of one of the first type and the second type impurities; and
the third region is doped with implants of another of the first type and the second type impurities.
20 . The device of claim 18 , wherein
the first surface region and the second surface region are doped with implants of at least one of a first type and a second type impurities; and
the first region and the third region are doped with implants of the first type impurities.
21 . The device of claim 18 , wherein
the first surface region is doped with implants of one of a first type and a second type impurities;
the second surface region is doped with implants of another of the first type and the second type impurities; and
the first region and the third region are doped with implants of the second type impurities.
22 . The device of claim 18 , wherein
the first surface region and the second surface region are doped with implants of a first type impurities; and
the first region and the third region are doped with implants of a second type impurities.
23 . The device of claim 22 , wherein
the first type impurities include p-type impurities; and
the second type impurities include n-type impurities.
24 . The device of claim 18 , further comprising:
a first contact region in the first surface region;
a second contact region in the second surface region; and
a third contact region in the third surface region, wherein the contact regions are arranged to receive a tunneling voltage.
25 . The device of claim 24 , wherein
the first contact region is a source terminal;
the second contact region is a drain terminal; and
the third surface region is a body terminal.
26 . The device of claim 24 , wherein
the tunneling-enhanced floating gate device is a field effect transistor (FET) comprising at least one of: a MOSFET, a FinFET, and a MESFET.
27 . The device of claim 24 , wherein
the tunneling-enhanced floating gate device is arranged to receive a tunneling voltage to adjust charges on the floating gate structure that is coupled to a read-out circuit of a memory cell.
28 . The device of claim 18 , further comprising:
at least one of a first field oxide region and a second field oxide region that are arranged to define boundaries of the n-well.
29 . The device of claim 18 , wherein
the second surface region and the third surface region are at least one of overlapping, abutting, and separated by another region.
30 . The device of claim 18 , wherein
the floating gate structure is arranged such that the first region and the first surface region are one of overlapping, non-overlapping, and approximately adjacent thereto.
31 . The device of claim 18 , wherein
the floating gate structure is arranged such that the third region and the second surface region are one of overlapping, non-overlapping, and approximately adjacent thereto.
32 . The device of claim 18 , wherein
the floating gate structure is adapted to be charged by at least one of: impact-ionized hot-electron injection, Fowler-Nordheim (FN) tunneling, channel hot-electron injection, and band-to-band tunneling induced electron injection.
33 . The device of claim 18 , wherein
the floating gate structure is adapted to be discharged by FN tunneling, impact-ionization induced hot-hole injection, and band-to-band tunneling induced hot-hole injection.
34 . The device of claim 18 , wherein
the tunneling-enhanced floating gate device is of Silicon-On-Insulator (SOI) type and the substrate comprises a relatively thin layer of Si deposited over a thin film of oxide embedded onto a relatively thick layer of Si.
35 . The device of claim 18 , wherein
the tunneling-enhanced floating gate device is of Silicon-On-Sapphire (SOS) type and the substrate comprises a relatively thin layer of Si over sapphire (Al 2 O 3 ).
36 . The device of claim 18 , wherein
the tunneling-enhanced floating gate device is of GaAs type and the substrate comprises a thin layer of Ga deposited over a layer of As.
37 . A method for creating a tunneling-enhanced floating gate device, comprising:
forming a substrate that includes impurities of p-type;
forming an n-well within the substrate that includes impurities of n-type;
forming a first surface region in the n-well;
forming a second surface region in the n-well;
forming a floating gate structure disposed over a region in the n-well defined by the first surface region and the second surface region, wherein the floating gate structure includes a first region, a centrally located second region that is doped with implants of n-type impurities, and a third region; and
forming a third surface region that is located about the second surface region away from the floating gate structure, wherein the third surface region is doped with implants of n-type impurities.
38 . The method of claim 37 , further comprising:
forming a first contact region in the first surface region;
forming a second contact region in the second surface region;
forming a third contact region in the third surface region, wherein the contact regions are arranged to receive a tunneling voltage; and
forming at least one of a first field oxide region and a second field oxide region that define boundaries of the n-well.
39 . The method of claim 37 , further comprising:
doping the first surface region and the second surface region with implants of at least one of a first type and a second type impurities;
doping the first region with implants of one of the first type and the second type impurities; and
doping the third region with implants of another of the first type and the second type impurities.
40 . The method of claim 37 , further comprising:
doping the first surface region and the second surface region with implants of at least one of a first type and a second type impurities; and
doping the first region and the third region with implants of the first type impurities.
41 . The method of claim 37 , further comprising:
doping the first surface region with implants of one of a first type and a second type impurities;
doping the second surface region with implants of another of the first type and the second type impurities; and
doping the first region and the third region with implants of one of the second type impurities.
42 . The method of claim 37 , further comprising:
doping the first surface region and the second surface region with implants of a first type impurities; and
doping the first region and the third region with implants of a second type impurities.
43 . The method of claim 42 , wherein
the first type impurities include p-type impurities; and
the second type impurities include n-type impurities.