Method for making a FET channel
View Patent ↗A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32 , each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and Si x Ge 1-x , wherein 78<x<92. The channel core 24 has a top surface 26 of width w c and an upstanding surface 28, 30 of height h c , preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26 , improving electrical conductivity and gate 18 control over the channel 16 . The height h c can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method. Embodiments and methods for FinFETs with one to four gates are disclosed.
1. A method for making a FET channel comprising:
providing a substrate and a first semiconductor material overlying the substrate;
defining a first channel core from the first semiconductor material, wherein the channel core defines a top surface spaced from the substrate and opposed first and second sidewalls between the substrate and the top surface;
disposing a layer of second semiconductor material to contact at least two of the top surface, the first sidewall and the second sidewall; and
disposing a gate oxide on at least two exterior surfaces of the second semiconductor material that are opposed to the at least two of the top surface, the first sidewall, and the second sidewall.
2. The method of claim 1 wherein the first semiconductor material comprises one of Si or Si x Ge 1-x and the second semiconductor material comprises the other of Si or Si x Ge 1-x .
3. The method of claim 1 wherein disposing a layer of second semiconductor material comprises masking and etching.
4. The method of claim 3 wherein defining a first channel core comprises defining a first and a second channel core spaced from one another, and disposing a layer of second semiconductor material comprises disposing said layer on the first channel core but not the second channel core.
5. The method of claim 1 wherein disposing a layer of second semiconductor material comprises disposing a carrier wafer with the layer of second semiconductor material over the first channel core, separating at least a portion of said layer from said carrier wafer, and removing said carrier wafer.
6. The method of claim 1 , wherein the first semiconductor material defines a first lattice structure and the second semiconductor, material has a second lattice structure that differs from that of the first.
7. The method of claim 1 , wherein disposing a gate oxide comprises disposing a gate oxide on the first and second sidewalls and the top surface.
8. The method of claim 1 , wherein disposing a gate oxide comprises disposing a gate oxide on the first and second sidewalls but not on the top surface.
9. A transistor made by the method of claim 1 .