Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

a semiconductor substrate;

a memory region provided on said semiconductor substrate; and

a logic region provided on said semiconductor substrate;

wherein said memory region includes:

a first transistor provided on said semiconductor substrate,

a first insulating layer covering said first transistor,

a plurality of first conductive plugs connected to a diffusion layer of said first transistor and terminated on an upper surface of said first insulating layer,

a capacitor element provided on said first insulating layer, and

a bit line provided on said first insulating layer;

wherein said logic region includes:

a second transistor provided on said semiconductor substrate and covered with said first insulating layer,

a plurality of second conductive plugs connected to a diffusion layer of said second transistor and terminated on an upper surface of said first insulating layer, and

an upper interconnect provided on said second conductive plug;

wherein said plurality of second conductive plugs includes a plug connected to said upper interconnect via at least one conductive plug; and

wherein said plurality of first conductive plugs includes a plug connected to said capacitor element, a plug connected to said bit line, and an isolated plug connected neither to said capacitor element nor to said bit line.

2. The semiconductor device according to claim 1 , wherein said plurality of second conductive plugs includes a plug connected to said upper interconnect via at least one conductive plug and an isolated plug not connected to said upper interconnect.

3. A semiconductor device comprising:

a semiconductor substrate;

a memory region provided on said semiconductor substrate; and

a logic region provided on said semiconductor substrate;

wherein said memory region includes:

a first transistor provided on said semiconductor substrate, a first insulating layer covering said first transistor,

a plurality of first conductive plugs connected to a diffusion layer of said first transistor and terminated on an upper surface of said first insulating layer,

a capacitor element provided on said first insulating layer, and

a bit line provided on said first insulating layer; said logic region includes:

a second transistor provided on said semiconductor substrate and covered with said first insulating layer,

a plurality of second conductive plugs connected to a diffusion layer of said second transistor and terminated on an upper surface of said first insulating layer, and

an upper interconnect provided on said second conductive plugs via a multilayer insulating layer;

wherein said plurality of first conductive plugs includes a plug connected to said capacitor element and a plug connected to said bit line and an isolated plug connected neither to said capacitor element nor to said bit line;

wherein said logic region includes a plurality of connected plugs and a plurality of isolated plugs;

wherein said plurality of connected plugs includes at least one of said second conductive plugs and at least one conductive plug that connects said one second conductive plug with said upper interconnect; and

wherein said plurality of isolated plugs includes at least another of said second conductive plugs, said plurality of isolated plugs are not connected to said upper interconnect and are terminated at a different level of said multilayer insulating layer than said plurality of connected plugs.

4. The semiconductor device according to claim 1 ,

wherein said memory region includes:

a plurality of capacitor contact plugs connected to said first conductive plugs and terminated on an upper surface of a second insulating layer provided on said first insulating layer, and

a plurality of bit contact plugs connected to said first conductive plugs;

said logic region includes a plurality of third conductive plugs connected to said second conductive plugs and terminated on an upper surface of said second insulating layer;

said plurality of bit contact plugs includes a plug connected to said bit line;

said plurality of third conductive plugs includes a plug connected to said upper interconnect; and

said plurality of capacitor contact plugs includes a plug connected to said capacitor element and an isolated plug not connected to said capacitor element.

5. The semiconductor device according to claim 3 ,

wherein said memory region includes:

a plurality of capacitor contact plugs connected to said first conductive plugs and terminated on an upper surface of a further insulating layer that is a layer of said multilayer insulating layer, and

a plurality of bit contact plugs connected to said first conductive plugs;

said logic region includes a plurality of third conductive plugs connected to said second conductive plugs and terminated on an upper surface of said further insulating layer;

said plurality of capacitor contact plugs includes a plug connected to said capacitor element;

said plurality of bit contact plugs includes a plug connected to said bit line; and

said plurality of connected plugs consists of said at least one second conductive plug, said third conductive plugs and at least one conductive plug that connects said third conductive plugs with said upper interconnect; and

at least one of said isolated plugs consists of said at least another second conductive plug and said third conductive plugs and is terminated on an upper surface of said further insulating layer.

6. The semiconductor device according to claim 1 , wherein said bit contact plug and said bit line are buried in a second insulating layer provided on said first insulating layer.

7. The semiconductor device according to claim 1 , wherein said capacitor element is located on said bit line.

8. The semiconductor device according to claim 1 , wherein said memory region includes a DRAM cell.

9. The semiconductor device according to claim 1 , wherein said logic region includes a peripheral circuit of said memory region.