Semiconductor device with power supply impurity region
View Patent ↗A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing method thereof. In a semiconductor device including MOS transistors each having an N-type impurity region 110 formed in a P-well 101 provided in a silicon substrate 100 thereof and including a GND contact 130 for supplying a GND potential to the P-well 101 , a portion of an impurity region 110 is etched and removed. Then, a P-type diffusion layer 131 for power supply is formed in the etched and removed region in the silicon substrate. Power supply to the P-well 101 is then performed via the GND contact 130 connected to the power supply diffusion layer 131.
1. A semiconductor device comprising:
transistor elements each including an impurity region formed in a well of one conductivity type provided in a semiconductor substrate thereof, the impurity region including a conductivity type opposite to the one conductivity type of the well, and the impurity region including a recessed portion;
contacts each supplying a predetermined potential to the well; and
a power supply impurity region disposed in the recessed portion in the semiconductor substrate,
wherein the power supply impurity region is adapted to supply power to the well.
2. The semiconductor device according to claim 1 , wherein the impurity region comprises a source/drain region of an MOS transistor including a lightly doped drain (LDD) structure, and the power supply impurity region is disposed beneath the recessed portion.
3. The semiconductor device according to claim 1 , wherein the impurity region comprises a high-concentration diffusion layer constituting a source/drain region of an MOS transistor, and
wherein the power supply impurity region is disposed beneath a recessed portion of the high-concentration diffusion layer.
4. The semiconductor device according to claim 1 , wherein a silicide layer is disposed on a surface of the power supply impurity region, and power supply to the power supply impurity region and the well is supplied via the silicide layer.
5. The semiconductor device according to claim 4 , wherein a memory cell is comprised of the transistor elements, and the power supply impurity region is provided for each of a plurality of memory cells formed on the semiconductor substrate.
6. The semiconductor device according to claim 4 , wherein the silicide layer, when in contact with the contacts and the power supply impurity region, is disposed below a gate electrode.
7. The semiconductor device according to claim 4 , wherein the silicide layer, when in contact with the contacts and the power supply impurity region, is disposed below an upper surface of an adjoining isolation layer.
8. The semiconductor device according to claim 4 , wherein the silicide layer is disposed above a bottom surface of the impurity region.
9. The semiconductor device according to claim 1 , wherein the power supply impurity region is disposed below the recessed portion of the impurity region.
10. The semiconductor device according to claim 1 , wherein the power supply impurity region comprises the one conductivity type.
11. The semiconductor device according to claim 1 , wherein the power supply impurity region is disposed between the impurity region, and an element isolation region.
12. A semiconductor device including a P-well and an N-well formed in a semiconductor substrate thereof, the semiconductor device comprising:
N-type MOS transistors disposed in the P-well and P-type MOS transistors disposed in the N-well;
a P-type impurity region disposed in a recessed portion of a source/drain region of each of the N-type MOS transistors;
an N-type impurity region disposed in a recessed portion of a source/drain region of each of the P-type MOS transistors; and
a predetermined potential is supplied to the P-well via the P-type impurity region and a predetermined potential is supplied to the N-well via the N-type impurity region.
13. The semiconductor device according to claim 12 , wherein a silicide layer is disposed on a surface of the P-type and N-type impurity regions, and power supply to the P-type and N-type impurity regions and the well is performed via the silicide layer.
14. The semiconductor device according to claim 13 , wherein a memory cell is comprised of the N-type and P-type MOS transistors, and the P-type impurity region is provided for each of a plurality of N-type memory cells formed on the semiconductor substrate, and the N-type impurity region is provided for each of a plurality of P-type memory cells formed on the semiconductor substrate.
15. A semiconductor device comprising:
transistor elements including an impurity region formed in a well of one conductivity type provided in a semiconductor substrate thereof, the impurity region including a conductivity type opposite to the one conductivity type of the well, and the impurity region including a recessed portion;
contacts supplying a predetermined potential to the well; and
a power supply impurity region of the one conductivity type disposed below the recessed portion of the impurity region,
wherein the power supply impurity region is adapted to supply power to the well.
16. The semiconductor device according to claim 15 , wherein the predetermined potential is supplied to the power supply impurity region and the well via a silicide layer.
17. The semiconductor device according to claim 16 , wherein the silicide layer is disposed on an upper surface of the power supply impurity region.
18. The semiconductor device according to claim 16 , wherein the silicide layer is disposed above a bottom surface of the impurity region.
19. The semiconductor device according to claim 16 , wherein the silicide layer is disposed on an upper surface of the impurity region.