Semiconductor device
View Patent ↗A memory region including a capacitor element, a logic region including a logic circuit, and a boundary region located between the memory region and the logic region are provided on a silicon substrate. The memory region includes a plurality of memory transistors and memory transistor connection plugs. The boundary region includes a dummy contact plug in the same layer as the memory transistor connection plugs and logic transistor connection plugs. The upper face of the dummy contact plug is covered with a second insulating layer. An end portion of a capacitor layer and an upper electrode is located closer to an inner region of the memory region than the dummy contact plug is.
1. A semiconductor device comprising:
a semiconductor substrate;
a memory region provided on said semiconductor substrate, said memory region including a first transistor provided on a main surface of said semiconductor substrate, a first insulating layer covering said first transistor, a capacitor element formed on said first insulating layer, and a plurality of capacitor contact plugs connecting a diffusion layer of said first transistor and said capacitor element;
a logic region provided on said semiconductor substrate, said logic region includes a second transistor provided on said semiconductor substrate and covered with said first insulating layer, an interconnect layer formed on said first insulating layer; and
a boundary region located between said memory region and said logic region, provided on said semiconductor substrate, said boundary region including a dummy contact plug having its upper surface covered with an insulating layer and located in the same layer as said capacitor contact plug;
wherein a conductive layer and a capacitor layer constituting said capacitor element are terminated at a position closer to an inner region of said memory region than said dummy contact plug is.
2. The semiconductor device according to claim 1 , further comprising:
a second insulating layer formed on said first insulating layer;
wherein said capacitor element includes a first conductive member that covers an inner wall of a through hole located on said capacitor contact plug and penetrating said second insulating layer, and is connected to an upper face of said capacitor contact plug, a second conductive member located with a separation above said first conductive member so as to fill said through hole, and said capacitor layer located between said first conductive member and said second conductive member; and
wherein an end portion of said second conductive member shared by a plurality of said capacitor elements is located closer to an inner region of said memory region than a region where said dummy contact plug is provided.
3. The semiconductor device according to claim 1 , further comprising a row including a plurality of said capacitor contact plugs and said dummy contact plug, said capacitor contact plugs and said dummy contact plug being linearly aligned with a spacing in said row, from said memory region toward said boundary region,
wherein an end portion of said row on the side of said boundary region is terminated at said dummy contact plug provided in said boundary region.
4. The semiconductor device according to claim 3 , wherein said capacitor contact plugs and said dummy contact plug are disposed at constant intervals in said row.
5. The semiconductor device according to claim 1 , wherein said capacitor element is a DRAM cell.
6. The semiconductor device according to claim 1 , wherein said logic region includes a peripheral circuit of said memory region.