Current mirrors having fast turn-on time
View Patent ↗A current mirror circuit providing a fast turn on time. A node within the circuit is held at a first voltage when the current mirror is off to permit the node voltage to quickly reach a necessary value when the current mirror circuit is turned on.
1. Circuitry comprising a current mirror controller for controlling current mirrors, the current mirror controller comprising:
a control node having a reference current therethrough;
a current mirror master connected to the control node and receiving the reference current, the current mirror master connected to the current mirrors;
a first switching device connected to a power supply controlling a state of the current mirror master;
a circuit module configured to control a voltage at the control node to a first voltage during a first operational mode; and
the circuit module configured to control the voltage at the control node to a second voltage during a second operational mode, wherein:
the first switching device controls the current mirror master to an on state during the second operational mode during which the current mirrors mirror the reference current;
a current produced by a one of the current mirrors is responsive to an area feature of the one of the current mirrors relative to the area feature of the current mirror master; and
the first operational mode comprises an off state for the current mirrors and the second operational mode comprises a current-supplying state for the current mirrors.
2. The circuitry of claim 1 , the current mirror controller further comprising a capacitor connected to the control node, wherein the circuit module controls a capacitor charge to the first voltage during the first operational mode and controls the capacitor charge to the second voltage during the second operational mode.
3. The circuitry of claim 1 wherein the current mirror master comprises a BJT having an emitter terminal connected to ground via a resistor, a collector terminal connected to the control node and a base terminal receiving drive current from the first switching device.
4. The circuitry of claim 1 wherein the first voltage is less than the second voltage.
5. The circuitry of claim 1 wherein the first switching device comprises a MOSFET supplying a drive current to the current minor master and to the current minors in the second operational mode, wherein in response to the drive current the current mirrors mirror the reference current.
6. The circuitry of claim 5 wherein the circuit module comprises a second switching device in series relationship with the first switching device controlling the first switching device in response to a control signal supplied to a control terminal of the second switching device, wherein in the first operational mode the control signal controls the second switching device to interrupt the drive current provided by the first switching device and in the second operational mode the control signal controls the second switching device to permit the first switching device to supply the drive current to the current mirror master, in response to which the current mirrors mirror the reference current.
7. The circuitry of claim 1 wherein the circuit module comprises:
a controllable current path from the control node to ground, wherein during the first operational mode the first current path comprises a first resistance, and wherein the first voltage is responsive to the first resistance; and
wherein during the second operational mode the controllable current path comprises a second resistance, and wherein the second voltage is responsive to the second resistance.
8. The circuitry of claim 1 , the current minor controller further comprising a switching device connected to the control node providing the reference current to the control node, wherein the switching device is responsive to a control signal controlling the reference current.
9. The circuitry of claim 1 wherein the current mirrors are operative to supply current to an amplifier during a data read mode of a disk drive data storage system.
10. The circuitry of claim 9 wherein the first operational mode comprises a non-read interval of the disk drive data storage system and the second operational mode comprises a data read interval of the disk drive data storage system.
11. The circuitry of claim 1 wherein the circuit module further comprises:
a second switching device in series relationship with the first switching device controlling the first switching device in response to a control signal supplied to a control terminal of the second switching device, wherein in the first operational mode the control signal controls the second switching device to interrupt drive current supplied by the first switching device to the current mirror master in response to which the current mirror master and the current mirrors are in an off condition;
wherein in the second operational mode the control signal controls the second switching device to permit the first switching device to supply drive current to the current mirror master in response to which the current mirror master and the current mirrors are in an on condition during which the current mirrors supply a current related to the reference current;
a control device having a control terminal connected to the control node and a current path therethrough, the control device operative in response to a signal supplied to the control terminal in response to which during the first operational mode the control device presents a closed current path;
a third switching device having a control terminal and a current path therethrough operative in response to a signal supplied to the control terminal, wherein in response to a control signal supplied to the control terminal thereof during the first operational mode the third switching device presents a dosed current path;
wherein the current path of the control device is in serial relationship with the current path of the third switching device;
a control transistor having a collector-emitter path from the control node to ground and having a base terminal, wherein during the first operational mode the third switching device and the control device cooperate to control the control transistor to an on condition to produce the first voltage at the control node; and
a fourth switching device having a control terminal and a current path therethrough operative in response to a signal supplied to the control terminal thereof, wherein during the second operational mode the fourth switching device presents a closed current path to short the base terminal of the control transistor to ground and turn off the control transistor causing the voltage at the control node to reach the second voltage.
12. The circuitry of claim 11 , the current mirror controller further comprising a capacitor connected between the control node and ground, wherein the capacitor charges to the second voltage when the control transistor is in the off state.
13. The circuitry of claim 1 wherein the circuit module further comprises:
a second switching device in series relationship with the first switching device controlling the first switching device in response to a control signal supplied to a control terminal of the second switching device, wherein in the first operational mode the control signal controls the second switching device to interrupt drive current supplied by the first switching device to the current mirror master in response to which the current mirror master and the current mirrors are in an off condition;
wherein in the second operational mode the control signal controls the second switching device to permit the first switching device to supply drive current to the current mirror master in response to which the current mirror master and the current mirrors are in an on condition during which the current mirrors supply a current related to the reference current;
a control device having a controllable current path therethrough and presenting a dosed current path during the first operational mode;
a third switching device having a controllable current path therethrough and, presenting a dosed current path during the first operational mode;
wherein the current path of the control device is in serial relationship with the current path of the third switching device;
a control transistor having a controllable current path therethrough between ground and the control node, wherein during the first operational mode the current paths of the third switching device and the control device are configured to control the control transistor to an on condition to produce the first voltage at the control node; and
a fourth switching device having a controllable current path therethrough and presenting a dosed current path during the second operational mode to control the control transistor to an off condition in response to which the voltage at the control node comprises the second voltage.
14. The circuitry of claim 1 , wherein the circuitry is a preamplifier for a disk drive data storage system, the circuitry further comprising:
an amplifier responsive to current produced by the current mirrors and further responsive to a voltage representing data bits read from the disk drive, wherein the amplifier amplifies the voltage representing the data bits.
15. The circuitry of claim 14 wherein the circuit module comprises:
a controllable current path from the control node to ground, wherein during the first operational mode the first current path comprises a first resistance, and wherein the first voltage is responsive to the first resistance; and
wherein during the second operational mode the controllable current path comprises a second resistance, and wherein the second voltage is responsive to the second resistance.
16. The circuitry of claim 14 wherein the first voltage is less than the second voltage.
17. An amplifier/buffer, comprising:
a differential amplifier;
a buffer responsive to the differential amplifier;
a plurality of current sources supplying current to the differential amplifier and to the buffer;
a current source master;
a node, wherein a turn-on time of the plurality of current sources is responsive to a voltage at the node;
a reference current, wherein a current produced by each one of the plurality of current sources is responsive to the reference current;
a module controlling a voltage at the node to effect the turn on time of the plurality of current sources; and
a capacitor connected to the node, wherein the module controls the voltage at the node by charging the capacitor such that a capacitor voltage comprises a first voltage when the amplifier/buffer is in an idle state and controls the capacitor voltage to a second voltage when the amplifier/buffer is in an on state.
18. The amplifier/buffer of claim 17 operative to receive signals during a read interval, wherein the signals represent data bits stored in a magnetic material, and wherein the module controls the voltage to a first voltage during non-read intervals and controls the voltage to a second voltage during read intervals.
19. The amplifier/buffer of claim 18 wherein the first voltage is less than the second voltage.
20. An differential amplifier, comprising
a pair of differentially-connected transistors responsive each responsive to a differential input signal;
a first and a second current source each supplying current to one of the transistors;
a current source master,
a node, wherein a turn-on time of the first and the second current sources is responsive to a voltage at the node;
a reference current, wherein a current produced by the first and the second current sources is responsive to the reference current,
a module controlling a voltage at the node to effect the turn on time of the first and the second current sources; and
a capacitor connected to the node, wherein the module controls the voltage at the node by charging the capacitor such that a capacitor voltage comprises a first voltage when the differential amplifier is in an idle state and controls the capacitor voltage to a second voltage when the differential amplifier is in an on state.
21. The amplifier of claim 20 wherein the first voltage is less than the second voltage.
22. A current mirror, comprising
a current mirror master,
a plurality of current mirrors responsive to the current mirror master;
a node connected to the current mirror master, wherein a turn-on time of the plurality of current mirrors is responsive to a voltage at the node;
a reference current through the node and the current mirror master, wherein a current produced by each one of the plurality of current mirrors is responsive to the reference current;
a module configured to control a voltage at the node to effect the turn on time of the plurality of current mirrors; and
a capacitor connected to the node, wherein the module controls the voltage at the node by charging the capacitor such that a capacitor voltage comprises a first voltage when the current mirror is in an idle state and controls the capacitor voltage to a second voltage when the current mirror is in an on state.
23. A method for controlling current minors, comprising
controlling a voltage at a control node to a first voltage during a first operational mode and to a second voltage during a second operational mode, wherein a capacitor is connected to the control node;
supplying a reference current through the control node to a current mirror master, wherein during the second operational mode the reference current is mirrored and scaled by the current mirrors;
charging the capacitor from the first voltage to the second voltage at an onset of the second operational mode such that after the capacitor is charged to the second voltage the current mirrors are turned on to mirror the reference current; and
using a capacitor connected to the control node, wherein the voltage at the node is controlled by charging the capacitor such that a capacitor voltage comprises a first voltage when the current minors are in an idle state and the capacitor voltage is controlled to a second voltage when the current minors are in an on state.