IP Library › Assignment 033663/0948
Patent Assignment
Reel/Frame 033663/0948

CERTIFICATE OF CONVERSION

Recorded: 2014-08-29 Received: 2014-08-29 Pages: 9
Assignor
AGERE SYSTEMS INC.
Executed: 2012-07-30
Assignee
AGERE SYSTEMS LLC
1110 AMERICAN PARKWAY NE, ALLENTOWN, PA, 18109, UNITED STATES
Covered Applications (100)
Systems and Methods for Low Latency Media Defect Detection
App. No. 13/368,599
→
Systems and Methods for Variable Compensated Fly Height Measurement
App. No. 13/326,493
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COMPENSATION FOR TRANSMISSION LINE LENGTH VARIATION IN A SERDES SYSTEM
App. No. 13/243,190
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METHODS OF FABRICATING A MEMBRANE WITH IMPROVED MECHANICAL INTEGRITY
App. No. 13/012,936
→
METHOD AND APPARATUS FOR EVALUATING PERFORMANCE OF A READ CHANNEL
App. No. 13/007,004
→
SYSTEMS AND METHODS FOR REDUCING LOW FREQUENCY LOSS IN A MAGNETIC STORAGE DEVICE
App. No. 12/992,943
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METHOD AND APPARATUS FOR REGULATING A POWER SUPPLY OF AN INTEGRATED CIRCUIT
App. No. 12/843,139
→
METHODS AND SYSTEMS FOR ESTIMATING TIME CORRESPONDING TO PEAK SIGNAL AMPLITUDE
App. No. 12/772,085
→
PROCESS AND TEMPERATURE TOLERANT NON-VOLATILE MEMORY
App. No. 12/756,401
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SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY
App. No. 12/682,162
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METHOD AND APPARATUS FOR EVALUATING PERFORMANCE OF A READ CHANNEL
App. No. 12/750,049
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SYSTEMS AND METHODS FOR VARIABLE FLY HEIGHT MEASUREMENT
App. No. 12/669,483
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PATH METRIC DIFFERENCE COMPUTATION UNIT FOR COMPUTING PATH DIFFERENCES THROUGH A MULTIPLE-STEP TRELLIS
App. No. 12/547,921
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PATH COMPARISON UNIT FOR DETERMINING PATHS IN A TRELLIS THAT COMPETE WITH A SURVIVOR PATH
App. No. 12/547,862
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RELIABILITY UNIT FOR DETERMINING A RELIABILITY VALUE FOR AT LEAST ONE BIT DECISION
App. No. 12/547,888
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METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING
App. No. 12/533,432
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METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING
App. No. 12/533,484
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METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE
App. No. 12/443,776
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TRACKING CIRCUIT FOR REDUCING FAULTS IN A MEMORY
App. No. 12/415,248
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SYSTEMS AND METHODS FOR DEFECTIVE MEDIA REGION IDENTIFICATION
App. No. 12/399,679
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SYSTEMS AND METHODS FOR RECOVERING INFORMATION FROM A DEFECTIVE MEDIUM
App. No. 12/399,750
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INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY
App. No. 12/372,196
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COMPENSATING TRANSMISSION LINE TO REDUCE SENSITIVITY OF PERFORMANCE DUE TO CHANNEL LENGTH VARIATION
App. No. 12/370,230
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SYSTEMS AND METHODS FOR CONTROLLING A DC MOTOR
App. No. 12/374,304
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Systems and Methods for Memory Efficient Repeatable Run Out Processing
App. No. 12/328,024
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MEMORY CIRCUIT HAVING REDUCED POWER CONSUMPTION
App. No. 12/276,576
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SYSTEMS AND METHODS FOR SECTOR ADDRESS MARK DETECTION
App. No. 12/270,786
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OUTPUT COMPENSATED VOLTAGE REGULATOR, AN IC INCLUDING THE SAME AND A METHOD OF PROVIDING A REGULATED VOLTAGE
App. No. 12/250,427
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SYSTEMS AND METHODS FOR LOW LATENCY MEDIA DEFECT DETECTION
App. No. 12/236,148
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SYSTEMS AND METHODS FOR COMPENSATING BASELINE WANDERING IN PERPENDICULAR MAGNETIC RECORDING
App. No. 12/233,659
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METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION
App. No. 12/200,106
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PROCESS AND TEMPERATURE TOLERANT NON-VOLATILE MEMORY
App. No. 12/194,028
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METHODS OF FABRICATING A MEMBRANE WITH IMPROVED MECHANICAL INTEGRITY
App. No. 12/185,305
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MEMORY DEVICE WITH REDUCED BUFFER CURRENT DURING POWER-DOWN MODE
App. No. 12/161,818
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EMBEDDED MEMORY REPAIR
App. No. 12/160,505
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SYSTEMS AND METHODS FOR USING INTRINSIC DATA FOR REGENERATING DATA FROM A DEFECTIVE MEDIUM
App. No. 12/111,867
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SYSTEMS AND METHODS FOR REDUCING ATTENUATION OF INFORMATION DERIVED FROM A DEFECTIVE MEDIUM
App. No. 12/111,889
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METHOD AND APPARATUS FOR ADJUSTING A POWER SUPPLY OF AN INTEGRATED CIRCUIT
App. No. 12/012,761
→
METHOD AND APPARATUS FOR REGULATING A POWER SUPPLY OF AN INTEGRATED CIRCUIT
App. No. 12/012,733
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MULTIPLE-LEVEL MEMORY WITH ANALOG READ
App. No. 12/023,092
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Methods and Apparatus for Map Detection with Reduced Complexity
App. No. 12/017,765
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MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY AND EFFICIENT PARTIAL WORD WRITE OPERATION
App. No. 11/994,740
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DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS
App. No. 11/968,942
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Methods and Apparatus for Detecting and Decoding Adaptive Equalization Training Frames
App. No. 11/967,463
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METHOD AND APPARATUS FOR REPAIRING UNCORRECTABLE DRIVE ERRORS IN AN INTEGRATED NETWORK ATTACHED STORAGE DEVICE
App. No. 11/967,248
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NOISE PREDICTION-BASED SIGNAL DETECTION AND CROSS-TALK MITIGATION
App. No. 11/962,409
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DYNAMIC RANDOM ACCESS MEMORY WITH LOW-POWER REFRESH
App. No. 11/962,035
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REDUCED LEAKAGE DRIVER CIRCUIT AND MEMORY DEVICE EMPLOYING SAME
App. No. 11/947,210
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LOW-POWER READ CHANNEL FOR MAGNETIC MASS STORAGE SYSTEMS
App. No. 11/982,261
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METHODS AND APPARATUS FOR DETERMINING RECEIVER FILTER COEFFICIENTS FOR A PLURALITY OF PHASES
App. No. 11/870,908
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INCREMENTAL TUNING PROCESS FOR ELECTRICAL RESONATORS BASED ON MECHANICAL MOTION
App. No. 11/869,997
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INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE CONTROL
App. No. 11/860,891
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SYSTEMS AND METHODS FOR IMPROVED SYNCHRONIZATION BETWEEN AN ASYNCHRONOUSLY DETECTED SIGNAL AND A SYNCHRONOUS OPERATION
App. No. 11/841,026
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DUAL-PORT MEMORY
App. No. 11/830,417
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SYSTEMS AND METHODS FOR FAX BASED DIRECTED COMMUNICATIONS
App. No. 11/781,364
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GENERALIZED BIST FOR MULTIPORT MEMORIES
App. No. 11/775,956
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MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY AND PREEMPTIVE PARTIAL WORD WRITE OPERATION
App. No. 11/756,011
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MEMORY CELL FOR CONTENT-ADDRESSABLE MEMORY
App. No. 11/743,163
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MEMORY DEVICE WITH ERROR CORRECTION BASED ON AUTOMATIC LOGIC INVERSION
App. No. 11/738,827
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INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY
App. No. 11/736,208
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METHOD AND APPARATUS FOR HOT CARRIER PROGRAMMED ONE TIME PROGRAMMABLE (OTP) MEMORY
App. No. 10/586,176
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METHODS AND APPARATUS FOR CONTROLLING WRITE DRIVER CURRENT
App. No. 11/576,486
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PROCESSING SERVO DATA HAVING DC LEVEL SHIFTS
App. No. 11/728,862
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METHOD AND APPARATUS FOR REDUCED-STATE VITERBI DETECTION IN A READ CHANNEL OF A MAGNETIC RECORDING SYSTEM
App. No. 11/691,847
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TECHNIQUES FOR DESIGNING WIDE BAND LOW NOISE AMPLIFIERS
App. No. 11/673,264
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SYSTEMS AND METHODS FOR PRIORITIZING ERROR CORRECTION DATA
App. No. 11/620,988
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CONTENT ADDRESSABLE MEMORIES (CAMS) BASED ON A BINARY CAM AND HAVING AT LEAST THREE STATES
App. No. 11/619,889
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METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A READ ONLY MEMORY DEVICE USING SHORTENED PRECHARGE PHASE
App. No. 11/619,344
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VIRTUAL PROFILES FOR STORAGE-DEVICE ARRAY ENCODING/DECODING
App. No. 11/544,442
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PING-PONG STATE MACHINE FOR STORAGE-DEVICE ARRAY
App. No. 11/544,456
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METHOD AND APPARATUS FOR DISK ADDRESS AND TRANSFER SIZE MANAGEMENT
App. No. 11/539,350
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BUFFER MANAGEMENT METHOD AND SYSTEM WITH ACCESS GRANT BASED ON QUEUE SCORE
App. No. 11/539,392
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BACK-ANNOTATION IN STORAGE-DEVICE ARRAY
App. No. 11/544,445
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METHOD AND APPARATUS FOR AUTOMATIC RATE IDENTIFICATION AND CHANNEL SYNCHRONIZATION IN A MASTER-SLAVE SETTING FOR HIGH DATA THROUGHPUT APPLICATIONS
App. No. 11/541,398
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METHOD AND APPARATUS FOR SCHEDULING DISK READ REQUESTS
App. No. 11/529,001
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SYSTEMS AND METHODS FOR GENERATING ERASURE FLAGS
App. No. 11/535,540
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SYSTEMS AND METHODS FOR IMPROVING DISK DRIVE SYNCHRONIZATION
App. No. 11/534,265
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APPARATUS AND METHOD FOR CONTROLLING COMMON MODE VOLTAGE OF A DISK DRIVE WRITE HEAD
App. No. 11/521,568
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METHOD AND APPARATUS FOR MEASURING RESISTANCE OF A RESISTIVE SENSOR
App. No. 11/520,493
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HIGH-SPEED REDUNDANT DISK CONTROLLER METHODS AND SYSTEMS
App. No. 11/518,544
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ACCELERATED SEARCHING FOR CONTENT-ADDRESSABLE MEMORY
App. No. 11/460,045
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ACCELERATED SINGLE-ENDED SENSING FOR A MEMORY CIRCUIT
App. No. 11/460,035
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PHASE INTERPOLATOR WITH OUTPUT AMPLITUDE CORRECTION
App. No. 11/479,749
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HEAD-SPECIFIC STANDBY MODES FOR DISK DRIVE PREAMPLIFIERS AND THE LIKE
App. No. 11/445,535
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ASYNCHRONOUS SERVO RRO DETECTION EMPLOYING INTERPOLATION
App. No. 11/442,815
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ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS
App. No. 11/420,177
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TRACK DEFECT MAP FOR A DISK DRIVE DATA STORAGE SYSTEM
App. No. 11/419,279
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Method and apparatus for measuring duty cycle based on data eye monitor
App. No. 11/434,686
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SYSTEMS AND METHODS FOR ESTIMATING TIME CORRESPONDING TO PEAK SIGNAL AMPLITUDE
App. No. 11/415,819
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SYSTEMS AND METHODS FOR ACCESSING DATA FROM A VARIABLE POLARITY HEAD ASSEMBLY
App. No. 11/408,825
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SYSTEMS AND METHODS FOR LOW POWER MULTI-RATE DATA PATHS
App. No. 11/394,028
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COMPENSATION OF POLARIZATION MODE DISPERSION IN SINGLE MODE FIBER FOR MAXIMUM-LIKELIHOOD SEQUENCE ESTIMATION
App. No. 11/378,900
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METHODS AND APPARATUS FOR REDUCED HARDWARE MULTIPLE VARIABLE VOLTAGE GENERATOR
App. No. 11/376,606
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DECODING TECHNIQUES FOR READ-ONLY MEMORY
App. No. 11/363,366
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LAYOUT TECHNIQUES FOR MEMORY CIRCUITY
App. No. 11/363,010
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METHOD AND APPARATUS FOR GENERATING ONE OR MORE CLOCK SIGNALS FOR A DECISION-FEEDBACK EQUALIZER USING DFE DETECTED DATA
App. No. 11/356,691
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METHOD AND APPARATUS FOR STORING SURVIVOR PATHS IN A VITERBI DETECTOR USING SYSTEMATIC POINTER EXCHANGE
App. No. 11/241,759
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METHOD AND APPARATUS FOR STORING SURVIVOR PATHS IN A VITERBI DETECTOR USING INPUT-DEPENDENT POINTER EXCHANGE
App. No. 11/241,761
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DIFFERENTIAL INPUT/DIFFERENTIAL OUTPUT CONVERTER CIRCUIT
App. No. 11/241,874
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VARIABLE THRESHOLD BIPOLAR SIGNAL PEAK DETECTOR
App. No. 11/234,840
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