Process and temperature tolerant non-volatile memory
View Patent ↗A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
1. A memory comprising:
at least one array of memory cells arranged in rows and columns; and
a plurality of sense amplifiers having inputs coupled to corresponding columns of the memory cells;
wherein at least one of the sense amplifiers has a keeper circuit therein adapted to provide an amount of current to the input of the sense amplifier depending on at least one of a temperature of the memory array and a process speed of the memory array.
2. The memory of claim 1 , wherein the keeper circuit is responsive to a temperature sensor and to a process speed detector.
3. The memory of claim 1 , wherein the at least one sense amplifier has an output and the keeper circuit is additionally responsive to the output of the at least one sense amplifier.
4. The memory of claim 1 , further comprising a storage element coupled to the keeper circuit;
wherein the storage element is adapted to store a value related to the process speed of the memory.
5. The memory of claim 2 , wherein the temperature sensor and the array of memory cells are formed in different substrates.
6. A memory comprising:
an array of memory cells arranged in N columns of memory cells and M rows of memory cells;
M select lines coupling to corresponding rows of memory cells;
N bit lines coupling to corresponding columns of memory cells;
an address decoder adapted to enable a selected one of the M select lines in response to an address; and
N sense amplifiers coupled to corresponding ones of the bit lines;
wherein at least one of the sense amplifier comprises:
a keeper circuit therein adapted to provide an amount of current to the input of the sense amplifier depending on at least one of a temperature of the memory array and a process speed of the memory array.
7. The memory of claim 6 , wherein the at least one sense amplifier further comprises:
a first precharge transistor adapted to couple the corresponding one of the bit lines to a power supply node in response to a first signal; and
an amplifier, having an output and an input, the input coupling to the corresponding bit line.
8. The memory of claim 7 , the at least one sense amplifier further comprises:
a coupling transistor adapted to couple the corresponding bit line to the input of the amplifier in response to a second signal.
9. The memory of claim 8 , further comprising:
a timing circuit, responsive to a clock signal, adapted to generate the first and second signals, the first and second signals being non-overlapping signals.
10. The memory of claim 7 , wherein the keeper circuit comprises:
a first transistor, responsive to the output of the amplifier, adapted to couple the input of the amplifier to an intermediate node; and
a second transistor adapted to selectively couple the intermediate node to the power supply node in response to a signal dependent on one of the process speed of the memory array or the temperature of the memory array.
11. The memory of claim 10 , the keeper circuit further comprising:
an additional transistor, responsive to the output of the amplifier, adapted to couple the intermediate node to the power supply node.
12. The memory of claim 10 , further comprising:
a temperature sensor adapted to generate the signal dependent on memory temperature.
13. The memory of claim 12 , wherein the temperature sensor and the memory array are formed in different substrates.
14. The memory of claim 12 , further comprising:
a process speed detector adapted to generate the signal dependent on process speed of the memory.
15. The memory of claim 10 , further comprising:
a storage element;
wherein the storage element is adapted to store a value related to process speed of the memory and provide the signal dependent on process speed of the memory.
16. The memory of claim 7 , wherein the amplifier is an inverting CMOS gate.
17. A memory comprising:
an array of memory cells arranged in N columns of memory cells and M rows of memory cells;
M select lines coupling to corresponding rows of memory cells;
N bit lines coupling to corresponding columns of memory cells;
an address decoder adapted to enable a selected one of the M select lines in response to an address;
N sense amplifiers coupled to corresponding ones of the bit lines;
a temperature sensor adapted to generate a signal related to temperature of the memory; and
a process speed detector adapted to generate a signal related to process speed of the memory;
wherein at least one of the sense amplifiers comprises:
a keeper circuit therein adapted to provide an amount of current to the input of the sense amplifier depending on at least one of the signal related to temperature of the memory and the signal related to process speed of the memory.
18. The memory of claim 17 ,
wherein the at least one sense amplifier further comprises:
a precharge transistor adapted to couple the corresponding one of the bit lines to a power supply node in response to a first signal; and
an amplifier, having an output and an input, the input coupling to the corresponding bit line.
19. The memory of claim 18 , wherein the keeper circuit comprises:
a first transistor, responsive to the output of the amplifier, adapted to couple the input of the amplifier to an intermediate node;
a second transistor adapted to selectively couple the intermediate node to the power supply node in response to the signal related to temperature of the memory; and
a third transistor adapted to selectively couple the intermediate node to the power supply node in response to the signal related to process speed of the memory.
20. The memory of claim 17 , the at least one sense amplifier further comprises:
a coupling transistor adapted to couple the corresponding bit line to the input of the amplifier in response to a second signal.
21. The memory of claim 20 , further comprising:
a timing circuit, responsive to a clock signal, adapted to generate the first and second signals.
22. The memory of claim 20 , wherein the first and second signals are non-overlapping signals.