Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.
1. An interface for use between a parallel bus and a serial bus, comprising:
a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of said serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of said serializer/deserializer circuits are slave circuits generating slave clock signals, wherein said master clock signal is distributed to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
a clock divider associated with said master circuit for selectively generating a master clock signal having one or more lower data rates than said reference clock; and
a frequency detector associated with each of said slave circuits for automatically detecting a rate of said master clock signal.
2. The interface of claim 1 , further comprising a data interleaver in each of said serializer/deserializer circuits to handle data interleaving for said lower data rates.
3. The interface of claim 1 , wherein said master circuit generates a double rate clock having a rate that is twice the rate of said master clock and wherein said double rate clock is distributed to said slave circuits.
4. The interface of claim 1 , wherein said slave circuits further comprise a multiplexer for selecting an appropriate clock signal based on rate identification information from said corresponding frequency detector.
5. The interface of claim 1 , wherein selected data rate information is provided only to said master circuit.
6. The interface of claim 1 , wherein said interface is configured to compensate for a clock skew by identifying a phase of said master clock.
7. A method for use between a parallel bus and a serial bus, comprising:
generating a plurality of clock signals using a plurality of serializer/deserializer circuits, wherein one of said serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of said serializer/deserializer circuits are slave circuits generating slave clock signals;
distributing said master clock signal to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
selectively generating a master clock signal having one or more lower data rates than said reference clock using a clock divider associated with said master circuit; and
automatically detecting a rate of said master clock signal using a frequency detector associated with each of said slave circuits.
8. The method of claim 7 , further comprising the step of performing data interleaving in each of said serializer/deserializer circuits for said lower data rates.
9. The method of claim 7 , further comprising the steps of generating a double rate clock in said master circuit having a rate that is twice the rate of said master clock and distributing said double rate clock to said slave circuits.
10. The method of claim 7 , further comprising the step of selecting an appropriate clock signal in said slave circuits based on rate identification information from said corresponding frequency detector.
11. The method of claim 7 , further comprising the step of providing selected data rate information only to said master circuit.
12. The method of claim 7 , further comprising the step of compensating for a clock skew by identifying a phase of said master clock.
13. An integrated circuit, comprising:
an interface for use between a parallel bus and a serial bus, comprising:
a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of said serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of said serializer/deserializer circuits are slave circuits generating slave clock signals, wherein said master clock signal is distributed to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
a clock divider associated with said master circuit for selectively generating a master clock signal having one or more lower data rates than said reference clock; and
a frequency detector associated with each of said slave circuits for automatically detecting a rate of said master clock signal.
14. The integrated circuit of claim 13 , further comprising a data interleaver in each of said serializer/deserializer circuits to handle data interleaving for said lower data rates.
15. The integrated circuit of claim 13 , wherein said master circuit generates a double rate clock having a rate that is twice the rate of said master clock and wherein said double rate clock is distributed to said slave circuits.
16. The integrated circuit of claim 13 , wherein said slave circuits further comprise a multiplexer for selecting an appropriate clock signal based on rate identification information from said corresponding frequency detector.
17. The integrated circuit of claim 13 , wherein selected data rate information is provided only to said master circuit.
18. The integrated circuit of claim 13 , wherein said interface is configured to compensate for a clock skew by identifying a phase of said master clock.