Integrated circuit feature definition using one-time-programmable (OTP) memory
View Patent ↗In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.
1. An integrated circuit (IC) comprising:
(a) two or more feature blocks adapted to be independently enabled or disabled to provide any one of a plurality of feature sets for the IC;
(b) two or more one-time-programmable (OTP) memory cells, one for each feature block, each OTP memory cell storing a value; and
(c) two or more feature control modules, one for each feature block, each feature control module adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell, wherein:
each of the two or more feature control modules comprises digital logic circuitry having (i) a first input based on the value stored in the corresponding OTP memory cell, and (ii) a second input; and
each of the two or more feature control modules is adapted to output to the corresponding feature block (i) a first substantially constant value to disable the feature block if the first input has a feature-disable value, and (ii) a signal corresponding to the second input to enable the feature block if the first input has a feature-enable value, wherein the second input is a clock signal.
2. The IC of claim 1 , further comprising a data latch for each feature block, wherein each data latch is:
(i) connected between the corresponding OTP memory cell and the corresponding feature control module; and
(ii) adapted to read the value stored in the corresponding OTP memory cell only once after turning on the IC and then continuously provide to the feature control module, when the IC is operating, a value corresponding to the value stored in the corresponding OTP memory cell.
3. The IC of claim 1 , wherein:
the digital logic circuitry is an AND gate;
if the first input has the feature-disable value then the feature control module outputs the first substantially constant value corresponding to a first control value; and
if the first input has the feature-enable value, then the feature control module outputs the clock signal.