Granted Patent B2

US 8,711,984 · App. 12/017,765 · Granted Apr 29, 2014

Abstract

Claims (24)

1. A soft output channel detector for processing a received signal comprised of a plurality data samples and generating log-likelihood ratios for a sequence of said data samples associated with N consecutive bits per clock cycle, comprising:

a plurality, D, of maximum a posteriori (MAP) detectors operating in parallel, wherein each MAP detector processes a plurality of branch metrics, wherein said plurality of branch metrics are based on substantially the entire sequence of said data samples and generates a corresponding log-likelihood ratio for at least one symbol associated with N consecutive bits, wherein N is greater than or equal to D.

2. The soft output channel detector of claim 1 , further comprising means for merging said log-likelihood ratio values to form an output sequence.

3. The soft output channel detector of claim 1 , wherein N is four and D is two, and wherein each of said two MAP detectors generates two log-likelihood ratio values per quarter-rate clock cycle.

4. The soft output channel detector of claim 1 , wherein each MAP detector calculates combined metrics for transitions in a set of current transitions and the MAP detector that generates the log-likelihood ratios for a given symbol has all possible values for that symbol constrained in the set of current transition labels.

5. The soft output channel detector of claim 4 , wherein the log-likelihood ratio for a given value of a symbol is the difference between a best combined metric and a best combined metric out of current transitions with that particular symbol value.

6. The soft output channel detector of claim 4 , wherein a first of said MAP detectors constrains two consecutive bits out of four bits and a second of said MAP detectors constrains an additional two out of said four bits.

7. The soft output channel detector of claim 6 , wherein a first MAP detector determines a log-likelihood ratio value for two out of said four bits and a second MAP detector determines a log-likelihood ratio value for an additional two out of said four bits.

8. The soft output channel detector of claim 6 , wherein said first and second MAP detectors are offset by two bits and wherein a branch metric input to said second MAP detector is delayed by two bits from said first MAP detector.

9. The soft output channel detector of claim 1 , wherein a backward detector that calculates backward state metrics starts from all zero state metrics and is unraveled to represent a best metric path leaving a current trellis state in the forward direction.

10. The soft output channel detector of claim 9 , wherein a forward detector calculates a best metric path leading to a forward state at time k, and combined metrics for states at time k-Q are formed by adding a delayed forward metric leading to a state at time k-Q with a backward metric representing a best metric path of length Q leaving the said state at time k-Q in the forward direction.

11. The soft output channel detector of claim 1 , wherein a complexity of said channel detector is reduced by removing a dependence on one or more bits in a metric.

12. The soft output channel detector of claim 11 , wherein said dependence on one or more bits is removed by selecting the value of the bits that corresponds to a best metric.

13. The soft output channel detector of claim 1 , wherein bits that are not constrained by a state are selected based on one or more of feedback and a best metric.

14. The soft output channel detector of claim 1 , wherein the symbols are mapping of one or more detected bits.

15. The soft output channel detector of claim 13 , wherein the mapping is (1⊕D).

16. The method of claim 1 , wherein a backward detector that calculates backward state metrics has fewer states than a forward detector that calculates forward state metrics.

17. The method of claim 1 , wherein one or more branches in a trellis processed by said MAP detectors corresponds to more than one bit per branch.

18. A method for processing a received signal comprised of a plurality data samples and for generating log-likelihood ratios for a sequence of said data samples associated with N consecutive bits per clock cycle, comprising:

generating log-likelihood ratios for symbols associated with N consecutive bits per clock cycle using a plurality, D, of maximum a posteriori (MAP) detectors operating in parallel, wherein each MAP detector processes a plurality of branch metrics, wherein said plurality of branch metrics are based on substantially the entire sequence of said data samples and generates a corresponding log-likelihood ratio for at least one symbol associated with N consecutive bits, wherein N is greater than or equal to D.

19. The method of claim 18 , wherein a backward detector that calculates backward state metrics starts from all zero state metrics and is unraveled to represent a best metric path leaving a current trellis state in the forward direction.

20. The method of claim 19 , wherein each clock cycle N samples are received, full-rate branch metrics with 2 S states are calculated for each sample and shared with all the detectors, where S is the channel memory length, and the i th MAP detector in the plurality of D parallel MAP detectors, with 0≦i≦D−1, calculates soft-output associated with N/D consecutive bits and comprises a forward detector for a radix 2 N trellis with 2 F states at time k=jN−iN/D, where j is an index associated with an input clock cycle and the number of bits in the state label is F, with S≧F≧N/D, and

the backward detector in the MAP detector with index i=0 in the plurality of D parallel MAP detectors selects 2 S best N-step backward path metrics leaving each of the 2 S states at time (j−1)N in the forward direction.

21. The method of claim 20 , wherein N is four and D is two, wherein each of said two MAP detectors generates two log-likelihood ratio values per quarter-rate clock cycle.

Assignments (13)