Memory device with error correction capability and preemptive partial word write operation
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
1. A memory device comprising:
a memory array having a plurality of memory cells; and
error correction circuitry coupled to the memory array and configured to process words retrieved from the memory array;
said memory device being configured to perform a partial word write operation wherein an error correction code encode process for a given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word, and further wherein if the error correction code decode process when, completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word.
2. The memory device of claim 1 wherein the error correction code encode process comprises modifying one or more bits of a given retrieved dataword in accordance with new data to be written by the partial word write operation and computing an error correction code word for the modified retrieved dataword.
3. The memory device of claim 1 wherein the error correction code decode process for the given retrieved word is performed at least in part in parallel with the error correction code encode process for the given retrieved word.
4. The memory device of claim 1 wherein the error correction code decode process and an associated correct process are removed from a critical timing path of the partial word write operation.
5. The memory device of claim 1 wherein the partial word write operation comprises a read phase and a write phase.
6. The memory device of claim 5 wherein the error correction code encode process and the error correction code decode process are performed at least in part in parallel with one another as part of the write phase of the partial word write operation.
7. The memory device of claim 6 wherein the write phase is interrupted if the error correction code decode process indicates an error in the given retrieved word.
8. The memory device of claim 7 wherein the write phase is interrupted in conjunction with generation of a flag that requests a no-operation cycle for the memory device.
9. The memory device of claim 8 wherein the requested no-operation cycle is utilized to restart and complete the write phase using a corrected word.
10. The memory device of claim 1 wherein the partial word write operation comprises at least one of a byte write operation and a bit write operation.
11. The memory device of claim 1 wherein the memory device comprises a stand-alone memory device.
12. The memory device of claim 1 wherein the memory device comprises an embedded memory device.
13. An integrated circuit comprising a memory device and additional circuitry coupled to the memory device, said memory device comprising:
a memory array having a plurality of memory cells; and
error correction circuitry coupled to the memory array and configured to process words retrieved from the memory array;
said memory device being configured to perform a partial word write operation wherein an error correction code encode process for a given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word, and further wherein if the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word.
14. The integrated circuit of claim 13 wherein said additional circuitry comprises a processor.
15. The integrated circuit of claim 13 wherein the error correction code decode process and an associated correct process are removed from a critical timing path of the partial word write operation.
16. A method for use in a memory device comprising a memory array having a plurality of memory cells, the memory device further comprising error correction circuitry coupled to the memory array and configured to process words retrieved from the memory array, the method comprising the step of:
performing a partial word write operation in which an error correction code encode process for a given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word, and further wherein if the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word.
17. The method of claim 16 wherein the partial word write operation comprises a read phase and a write phase, the method further including the step of interrupting the write phase if the error correction code decode process indicates an error in the given retrieved word.
18. The method of claim 17 wherein the step of interrupting the write phase further comprises the step of generating in conjunction with the interruption of the write phase a flag that requests a no-operation cycle for the memory device.
19. The method of claim 18 further comprising the step of utilizing the no-operation cycle to restart and complete the write phase using a corrected word.
20. An article of manufacture comprising a processor-readable storage medium having embodied therein software code for implementing a method for use in a memory device comprising a memory array having a plurality of memory cells, the memory device further comprising error correction circuitry coupled to the memory array and configured to process words retrieved from the memory array, the method comprising the step of:
performing a partial word write operation in which an error correction code encode process for a given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word, and further wherein if the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word.
21. A memory device comprising:
a memory array having a plurality of memory cells; and
error correction circuitry coupled to the memory array and configured to process datawords and error correction words retrieved from the memory array;
said memory device being configured to perform a partial word write operation in which a first dataword and an associated first error correction word are retrieved from the memory array, and one or more bits of the first dataword are modified to produce a second dataword, wherein a second error correction word is determined for the second dataword before a determination is made based on the first error correction word as to whether or not the first dataword contains an error.
22. A method for use in a memory device comprising a memory array having a plurality of memory cells, the memory device further comprising error correction circuitry coupled to the memory array and configured to process datawords and error correction words retrieved from the memory array, the method comprising the step of:
performing a partial word write operation in which a first dataword and an associated first error correction word are retrieved from the memory array, and one or more bits of the first dataword are modified to produce a second dataword, wherein a second error correction word is determined for the second dataword before a determination is made based on the first error correction word as to whether or not the first dataword contains an error.