Methods and apparatus for serializer/deserializer transmitter synchronization
Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.
1. A method for synchronizing a plurality of channels in one or more serializer/deserializer devices, comprising:
generating a synchronization request in one or more of said channels;
generating an enable signal in response to said synchronization request; and
generating a gated synchronization signal for only one or more periods of a synchronization signal in response to said enable signal.
2. The method of claim 1 , further comprising the step of deasserting said gated synchronization signal after said one or more periods of a synchronization signal.
3. The method of claim 1 , wherein said gated synchronization signal is a non-continuous signal.
4. The method of claim 1 , wherein said gated synchronization signal synchronizes only said one or more channels that requested said synchronization.
5. The method of claim 4 , wherein said one or more channels request said synchronization upon a power up or a change in data rate.
6. The method of claim 4 , further comprising the step of enabling said gated synchronization signal in a given channel only if said given channel has requested said synchronization.
7. The method of claim 1 , wherein said enable signal selectively enables said gated synchronization signal.
8. The method of claim 1 , wherein said generating step generates said gated synchronization signal for a limited duration.
9. A serializer/deserializer device, comprising:
a clock generator for generating a synchronization signal; and
a plurality of communication channels that transmit serial data, wherein each of said channels comprise a synchronization circuit comprising:
a sync request block for generating a synchronization request;
a first logic circuit for generating an enable signal in response to said synchronization request; and
a second logic circuit for generating, in response to said enable signal, a gated synchronization signal for only one or more periods of a synchronization signal.
10. The serializer/deserializer device of claim 9 , wherein said second logic circuit deasserts said gated synchronization signal after said one or more periods of a synchronization signal.
11. The serializer/deserializer device of claim 9 , wherein said gated synchronization signal is a non-continuous signal.
12. The serializer/deserializer device of claim 9 , wherein said gated synchronization signal synchronizes only said one or more channels that requested said synchronization.
13. The serializer/deserializer device of claim 12 , wherein said one or more channels request said synchronization upon a power up or a change in data rate.
14. The serializer/deserializer device of claim 12 , further comprising the step of enabling said gated synchronization signal in a given channel only if said given channel has requested said synchronization.
15. The serializer/deserializer device of claim 9 , wherein said enable signal selectively enables said gated synchronization signal.
16. The serializer/deserializer device of claim 9 , wherein said second logic circuit generates said gated synchronization signal for a limited duration.
17. The serializer/deserializer device of claim 9 , wherein said sync request block is embodied on an integrated circuit.
18. The serializer/deserializer device of claim 9 , wherein said first logic circuit is an AND gate that receives a synchronization signal and a signal from a finite state machine.
19. The serializer/deserializer device of claim 9 , wherein said second logic circuit is an AND gate that receives a synchronization request from a given channel.
20. The serializer/deserializer device of claim 9 , wherein said clock generator is a phase locked loop circuit.