Process and temperature tolerant non-volatile memory
View Patent ↗A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
1. A memory comprising:
an array of memory cells arranged in N columns of memory cells and M rows of memory cells;
M select lines coupling to corresponding rows of memory cells;
N bit lines coupling to corresponding columns of memory cells, wherein M and N are positive integers;
an address decoder adapted to enable a selected one of the M select lines in response to an address; and
N sense amplifiers coupled to corresponding ones of the bit lines;
wherein at least one of the sense amplifier comprises:
a first precharge transistor adapted to couple the corresponding one of the bit lines to a power supply node in response to a first signal;
an amplifier, having an output and an input, the input coupling to the corresponding bit line;
a first transistor, responsive to the output of the amplifier, adapted to couple the input of the amplifier to an intermediate node; and
a second transistor adapted to selectively couple the intermediate node to the power supply node in response to a signal dependent on one of process speed of the memory or temperature of the memory.
2. The memory of claim 1 , further comprising:
a first coupling transistor adapted to couple the corresponding bit line to the input of the amplifier in response to a second signal.
3. The memory of claim 2 , further comprising:
a timing circuit, responsive to a clock signal, adapted to generate the first and second signals, the first and second signals being non-overlapping signals.
4. The memory of claim 1 , further comprising:
an additional array of memory cells arranged in columns and rows, the columns of memory cells coupling to corresponding additional bit lines;
wherein the at least one sense amplifier further comprises:
a first coupling transistor, responsive to the address decoder, adapted to couple the corresponding bit line of the memory cells to the input of the amplifier;
a second coupling transistor, responsive to the address decoder, adapted to couple a corresponding one of the additional bit lines to the input of the amplifier; and
a second precharge transistor adapted to couple a corresponding one of the additional bit lines to the power supply node in response to the first signal;
wherein the address decoder, in response to the second signal, is further adapted to enable one of the first or second coupling transistors.
5. The memory of claim 1 , wherein at least one memory cell comprises an access transistor and a fuse.
6. The memory of claim 1 , wherein at least one memory cell comprises a floating-gate transistor.
7. The memory of claim 1 , further comprising:
an additional transistor, responsive to the output of the amplifier, adapted to couple the intermediate node to the power supply node.
8. The memory of claim 1 , further comprising:
a temperature sensor adapted to generate the signal dependent on memory temperature.
9. The memory of claim 8 , wherein the temperature sensor and the memory array are formed in different substrates.
10. The memory of claim 1 , further comprising:
a process speed detector adapted to generate the signal dependent on process speed of the memory.
11. The memory of claim 1 , further comprising:
a storage element;
wherein the storage element is adapted to store a value related to process speed of the memory and provide the signal dependent on process speed of the memory.
12. The memory of claim 1 , wherein the amplifier is an inverting CMOS gate.
13. The memory of claim 1 , further comprising:
an additional precharge transistor adapted to couple the input of the amplifier to the power supply node in response to the first signal.
14. The memory of claim 1 , wherein the address decoder is additionally response to the first signal and the address decoder enables a selected one of the M select lines in response to the first signal and the address.
15. A memory comprising:
an array of memory cells arranged in N columns of memory cells and M rows of memory cells;
M select lines coupling to corresponding rows of memory cells;
N bit lines coupling to corresponding columns of memory cells, wherein M and N are positive integers;
an address decoder adapted to enable a selected one of the M select lines in response to an address;
N sense amplifiers coupled to corresponding ones of the bit lines;
a temperature sensor adapted to generate a signal related to temperature of the memory; and
a process speed detector adapted to generate a signal related to process speed of the memory;
wherein at least one of the sense amplifier comprises:
a precharge transistor adapted to couple the corresponding one of the bit lines to a power supply node in response to a first signal;
an amplifier, having an output and an input, the input coupling to the corresponding bit line;
a first transistor, responsive to the output of the amplifier, adapted to couple the input of the amplifier to an intermediate node;
a second transistor adapted to selectively couple the intermediate node to the power supply node in response to the signal related to temperature of the memory; and
a third transistor adapted to selectively couple the intermediate node to the power supply node in response to the signal related to process speed of the memory.
16. The memory of claim 15 , further comprising:
a coupling transistor adapted to couple the corresponding bit line to the input of the amplifier in response to a second signal.
17. The memory of claim 16 , further comprising:
a timing circuit, responsive to a clock signal, adapted to generate the first and second signals, the first and second signals being non-overlapping signals.