Integrated circuit feature definition using one-time-programmable (OTP) memory
View Patent ↗In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.
1. An integrated circuit (IC) comprising:
(a) two or more feature blocks adapted to be independently enabled or disabled to provide any one of a plurality of feature sets for the IC;
(b) two or more one-time-programmable (OTP) memory cells, one for each feature block, each OTP memory cell storing a value;
(c) two or more feature control modules, one for each feature block, each feature control module adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell; and
(d) a data latch for each feature block, wherein each data latch is:
(i) connected between the corresponding OTP memory cell and the corresponding feature control module; and
(ii) adapted to read the value stored in the corresponding OTP memory cell only once after the IC is turned on and then continuously provide to the feature control module, when the IC is operating, a value corresponding to the value stored in the corresponding OTP memory cell.
2. The IC of claim 1 , wherein:
at least one of the two or more feature control modules comprises digital logic circuitry having (i) a first input based on the value stored in the corresponding OTP memory cell, and (ii) a second input that is different from the first input; and
the at least one feature control module is adapted to output to the corresponding feature block (i) a first substantially constant value to disable the feature block if the first input has a feature-disable value, and (ii) a signal corresponding to the second input to enable the feature block if the first input has a feature-enable value.
3. The IC of claim 1 , wherein the feature control module comprises:
(a) a first transistor connected between a power-supply voltage and an output provided to the corresponding feature block to enable or disable the feature block; and
(b) a second transistor connected between the output and a reference voltage, wherein the gates of the first and second transistors are connected to an input signal, which is based on the value stored in the corresponding OTP memory cell, such that the output is (i) substantially equal to the power-supply voltage if the input signal has a first control value, and (ii) substantially equal to the reference voltage if the input signal has a second control value.
4. The IC of claim 3 , wherein the reference voltage is ground voltage.
5. The IC of claim 3 , wherein the first and second transistors are CMOS transistors.
6. The IC of claim 5 , wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
7. The IC of claim 1 , wherein the OTP memory cells are CMOS OTP memory cells.
8. The IC of claim 1 , wherein:
the two or more feature blocks include a first feature block and a second feature block; and
the first feature block provides a first feature set for the IC that is different from a second feature set for the IC provided by the second feature block.
9. A method for providing any one of a plurality of feature sets for an integrated circuit (IC), wherein the IC comprises (i) two or more feature blocks adapted to be independently enabled or disabled, (ii) two or more one-time-programmable (OTP) memory cells, one for each feature block, each OTP memory cell storing a value, and (iii) a data latch for each feature block, each data latch connected between the corresponding OTP memory cell and the corresponding feature block, the method comprising, for each feature block:
(a) receiving the value stored in the corresponding OTP memory cell, wherein step (a) comprises:
(i) reading, by the corresponding data latch, the value stored in the corresponding OTP memory cell only once after the IC is turned on; and
(ii) continuously receiving, from the corresponding data latch, a value corresponding to the value stored in the corresponding OTP memory cell; and
(b) controlling the feature block to enable or disable the feature block based on the value stored in the corresponding OTP memory cell.
10. The method of claim 9 , further comprising independently setting each OTP memory cell to store the value to enable or disable the corresponding feature block.
11. The method of claim 9 , further comprising, for each feature block:
receiving a first input based on the value stored in the corresponding OTP memory cell;
receiving a second input that is different from the first input;
outputting a first substantially constant value to disable the feature block if the first input has a feature-disable value; and
outputting a signal corresponding to the second input to enable the feature block if the first input has a feature-enable value.
12. The method of claim 11 , wherein the second input is a clock signal.
13. The method of claim 12 , comprising, for each feature block:
outputting the feature-disable value, if the first input has the feature-disable value; and
outputting the clock signal, if the first input has the feature-enable value.
14. The method of claim 9 , wherein the OTP memory cells are CMOS OTP memory cells.
15. The method of claim 9 , wherein:
the two or more feature blocks include a first feature block and a second feature block; and
the first feature block provides a first feature set for the IC that is different from a second feature set for the IC provided by the second feature block.
16. An integrated circuit (IC) comprising:
(a) two or more feature blocks adapted to be independently enabled or disabled to provide any one of a plurality of feature sets for the IC;
(b) two or more one-time-programmable (OTP) memory cells, one for each feature block, each OTP memory cell storing a value; and
(c) two or more feature control modules, one for each feature block, each feature control module adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell, wherein:
at least one of the two or more feature control modules comprises digital logic circuitry having (i) a first input based on the value stored in the corresponding OTP memory cell, and (ii) a second input that is different from the first input; and
the at least one feature control module is adapted to output to the corresponding feature block (i) a first substantially constant value to disable the feature block if the first input has a feature-disable value, and (ii) a signal corresponding to the second input to enable the feature block if the first input has a feature-enable value.
17. The IC of claim 16 , wherein:
(1) the feature control module comprises:
(a) a first transistor connected between a power-supply voltage and an output provided to the corresponding feature block to enable or disable the feature block; and
(b) a second transistor connected between the output and a reference voltage, wherein the gates of the first and second transistors are connected to an input signal, which is based on the value stored in the corresponding OTP memory cell, such that the output is (i) substantially equal to the power-supply voltage if the input signal has a first control value, and (ii) substantially equal to the reference voltage if the input signal has a second control value
(2) the first and second transistors are CMOS transistors, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor; and
(3) the OTP memory cells are CMOS OTP memory cells.
18. A method for providing any one of a plurality of feature sets for an integrated circuit (IC), wherein the IC comprises (i) two or more feature blocks adapted to be independently enabled or disabled and (ii) two or more one-time-programmable (OTP) memory cells, one for each feature block, each OTP memory cell storing a value, the method comprising, for each feature block:
(a) receiving the value stored in the corresponding OTP memory cell;
(b) controlling the feature block to enable or disable the feature block based on the value stored in the corresponding OTP memory cell;
(c) receiving a first input based on the value stored in the corresponding OTP memory cell;
(d) receiving a second input that is different from the first input;
(e) outputting a first substantially constant value to disable the feature block if the first input has a feature-disable value; and
(f) outputting a signal corresponding to the second input to enable the feature block if the first input has a feature-enable value.
19. The method of claim 18 , wherein the second input is a clock signal, comprising, for each feature block:
outputting the feature-disable value, if the first input has the feature-disable value; and
outputting the clock signal, if the first input has the feature-enable value.
20. The method of claim 18 , wherein the OTP memory cells are CMOS OTP memory cells.