Memory device with reduced buffer current during power-down mode
View Patent ↗A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.
1. A memory device comprising:
a memory array;
at least one buffer coupled to the memory array; and
test circuitry coupled to the buffer;
wherein the buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry;
wherein the control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device; and
wherein the buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by said buffer in the power-down mode of operation.
2. The memory device of claim 1 wherein said buffer comprises an input data buffer.
3. The memory device of claim 1 wherein said buffer comprises an address buffer.
4. The memory device of claim 1 wherein said test circuitry comprises built-in self-test circuitry of the memory device.
5. The memory device of claim 1 wherein said test circuitry comprises a first logic gate having first and second inputs for receiving the test signal and power-down signal, respectively.
6. The memory device of claim 5 wherein said test circuitry further comprises a second logic gate having a first input for receiving an output of the first logic gate and a second input for receiving the power-down signal.
7. The memory device of claim 6 wherein the control signal comprises an output of at least one of the first and second logic gates.
8. The memory device of claim 6 wherein the first and second logic gates comprise NAND gates.
9. The memory device of claim 6 wherein the first and second logic gates comprise NOR gates.
10. The memory device of claim 1 wherein the current reduction circuitry comprises a field effect transistor having source and drain terminals coupled between a supply node of the buffer and the given output of the buffer, and a gate terminal which receives the control signal from the test circuitry.
11. The memory device of claim 10 wherein the source and drain terminals are coupled between a ground terminal of the buffer and the given output of the buffer.
12. The memory device of claim 10 wherein the source and drain terminals are coupled between a VDD terminal of the buffer and the given output of the buffer.
13. The memory device of claim 1 wherein the memory device comprises a stand-alone memory device.
14. The memory device of claim 1 wherein the memory device comprises an embedded memory device.
15. An integrated circuit comprising the memory device of claim 1 .
16. A buffer for use in a memory device comprising a memory array and test circuitry, the buffer comprising:
switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry; and
current reduction circuitry coupled to the switching circuitry and responsive to the control signal for reducing an amount of current consumed by the buffer in a power-down mode of operation of the memory device;
wherein the control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of the power-down mode of operation.
17. An integrated circuit comprising the buffer of claim 16 .
18. A method for use in a memory device comprising a buffer, a memory array and test circuitry, the method comprising the steps of:
multiplexing first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry, wherein the control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device; and
reducing an amount of current consumed by said buffer in the power-down mode of operation responsive to the control signal.
19. The method of claim 18 wherein the reducing step comprises changing a conduction state of a field effect transistor in said buffer, the field effect transistor having source and drain terminals coupled between a supply node of the buffer and the given output of the buffer, and a gate terminal which receives the control signal from the test circuitry.
20. A non-transitory computer-readable storage medium comprising executable program code for implementing the method of claim 18 .