Method and apparatus for iterative error-erasure decoding
View Patent ↗Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.
1. A system for decoding a signal, comprising:
a memory; and
at least one processor, coupled to the memory, operative to:
obtain a plurality of symbols associated with said signal and one or more corresponding reliability values;
perform a first round of error-erasure decoding using a plurality of first erasure sets, wherein each of said first erasure sets comprises k erasures taken from a shortened erasure list comprised of L′ symbols; and
upon a predefined error condition, perform a second round of error-erasure decoding using one erasure set comprising n erasures taken from an erasure list comprised of L symbols, where n is larger than k and L larger than L′.
2. The system of claim 1 , wherein said processor is further configured to employ at least one threshold to mark K candidates having reliability values that satisfy said threshold, and sort said K candidates to determine a number N of most unreliable candidates, where K is greater than N.
3. The system of claim 1 , wherein said processor is further configured to generate one or more reliability values using a soft-output detector, compare said one or more reliability values to at least one threshold, and include symbols in an erasure list that satisfy said threshold.
4. The system of claim 1 , wherein said processor is further configured to generate all possible erasure sets of k symbols from said erasure list comprised of L′ symbols.
5. The system of claim 1 , wherein said error-erasure decoding comprises Reed-Solomon decoding.
6. The system of claim 1 , wherein said processor is further configured to perform a pre-processing round of error-erasure decoding prior to said first round, wherein said pre-processing round comprises:
generating at least one erasure list comprised of M symbols;
constructing one erasure set comprising j erasures taken from said at least one erasure list of size M; and
performing error-erasure decoding for said one erasure set, where L>L′>M and n>k>j.
7. The system of claim 6 , wherein said processor is further configured to:
increment said value of j if a substantial decoding failure is detected;
repeat said constructing and performing steps if j does not exceed M.
8. The system of claim 1 , wherein said processor is further configured to construct at least one erasure set that includes L″ erased symbols and additional erasures taken from an erasure list.
9. The system of claim 8 , wherein said L″ erased symbols are identified using feedback information.
10. The system of claim 1 , wherein said processor performs said first round of error-erasure decoding by:
generating at least one shortened erasure list comprised of L′ symbols;
constructing a plurality of first erasure sets, wherein each of said first erasure sets comprises k erasures taken from said shortened erasure list;
performing error-erasure decoding for said first erasure sets until a first erasure set is found for which there is no substantial decoding failure.
11. The system of claim 10 , wherein said plurality of first erasure sets comprising k erasures is constructed by erasing the M most unreliable symbols from said at least one shortened erasure list, and taking k−M additional erasures from the remaining L′−M symbols of said at least one shortened erasure list.
12. The system of claim 10 , wherein said processor is further configured to:
increment said value of k if a substantial decoding failure is detected; and
repeat said constructing and performing steps if k does not exceed L′.
13. The system of claim 1 , wherein said second round of error-erasure decoding further comprises:
generating at least one erasure list comprised of L symbols, where L is greater than L′;
constructing one erasure set comprising n erasures taken from said one erasure list of size L; and
performing error-erasure decoding for said one erasure set.
14. The system of claim 13 , wherein said processor is further configured to:
increment said value of n if a substantial decoding failure is detected for said error-erasure decoding of said one erasure set; and
repeat said constructing and performing steps until said value of n exceeds said value of L.
15. The system of claim 1 , wherein said predefined error condition comprises k exceeding L′.