Granted Patent B2

US 7,821,730 · App. 12/233,659 · Granted Oct 26, 2010

Abstract

Claims (53)

1. A data processing circuit, wherein the circuit comprises:

a digital filter, wherein the digital filter receives a series of digital samples and provides a filtered output;

a data detector, wherein the data detector receives the filtered output and performs a data detection on the filtered output to create a detected output;

a first summation element, wherein the first summation element subtracts the filtered output from the detected output to create an error signal;

a second summation element, wherein the second summation element subtracts the error signal from the filtered output to create a wander basis signal; and

a baseline correction feedback circuit, wherein the baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal, and wherein a derivative of the wander compensation signal is provided as feedback to the digital filter.

2. The circuit of claim 1 , wherein the digital filter is a digital finite impulse response filter.

3. The circuit of claim 2 , wherein the derivative of the wander compensation signal is operable to adjust a tap of the digital finite impulse response filter.

4. The circuit of claim 1 , wherein the circuit further comprises:

an analog input signal;

a preamplifier, wherein the preamplifier receives the analog input signal, amplifies the analog input signal, high pass filters the analog input signal, and provides an amplified input signal; and

an analog to digital converter, wherein the analog to digital converter receives the amplified input signal and provides the series of digital samples corresponding to the amplified input signal.

5. The circuit of claim 4 , wherein the analog input signal is derived from a magnetic storage medium written using a perpendicular recording approach.

6. The circuit of claim 4 , wherein low frequency information included in the analog input signal is eliminated by the high pass filtering of the preamplifier.

7. The circuit of claim 1 , wherein the data detector is a Viterbi algorithm data detector.

8. The circuit of claim 1 , wherein the data detector is a low density parity check detector.

9. The circuit of claim 1 , wherein the circuit further includes:

a delay block that transfers the filtered output to the first summation element.

10. The circuit of claim 9 , wherein the latency through the delay block is approximately equivalent to the latency between the filtered output and an ideal output.

11. The circuit of claim 1 , wherein the circuit further comprises:

an accumulator circuit, wherein the accumulator circuit accumulates a plurality of the error signal, and wherein the accumulator circuit provides an accumulation signal; and

a third summation element, wherein the third summation element aggregates the wander compensation signal with the accumulation signal to create the derivative of the wander compensation signal.

12. The circuit of claim 1 , wherein the baseline correction feedback circuit is a low pass digital filter.

13. A method for low latency baseline wandering compensation in relation to perpendicular recording data, the method comprising:

receiving an analog input signal;

performing an analog to digital conversion of the analog input signal to create a series of digital samples;

digitally filtering the series of digital samples based on a feedback signal to create a filtered digital output;

performing a data detection on the filtered digital output to create a detected output;

delaying the filtered digital output by a time period to create a delayed, filtered digital output;

subtracting the delayed, filtered digital output from the detected output to create an error signal;

subtracting the error signal from the filtered digital output to create a wander basis signal; and

low pass filtering the wander basis signal to create a wander compensation signal, wherein the feedback signal is a derivative of the wander compensation signal.

14. The method of claim 13 , wherein the method further comprises:

accumulating a number of instances of the error signal to create an accumulation signal; and

aggregating the accumulation signal and the wander compensation signal, wherein the derivative of the wander compensation signal is the result of aggregating the accumulation signal and the wander compensation signal.

15. The method of claim 13 , wherein the data detection is a Viterbi algorithm data detection.

16. The method of claim 15 , wherein the time period is approximately equivalent to the latency associated with the Viterbi algorithm data detection.

17. The method of claim 13 , wherein the analog input signal is received from a preamplifier that includes a high pass filter.

18. The method of claim 17 , wherein the input to the preamplifier is derived from a magnetic storage medium including information with a low frequency component stored in accordance with a perpendicular recording approach, and wherein the low frequency component is removed by the high pass filter.

19. A data storage device, the data storage device comprising:

a magnetic storage medium including information stored in accordance with a perpendicular recording approach;

a read/write head assembly disposed in relation to the magnetic storage medium, wherein the read/write head assembly is operable to sense the information on the magnetic storage medium and to provide an analog input signal representing the sensed information, and wherein the analog input signal includes low frequency data;

a preamplifier including a high pass filter, wherein the preamplifier receives the analog input signal and provides an amplified input signal corresponding to the analog input signal without the low frequency data;

an analog to digital converter, wherein the analog to digital converter receives the amplified input signal and provides a series of digital samples corresponding to the analog input signal;

a digital filter, wherein the digital filter receives the series of digital samples and provides a corresponding filtered output based on a feedback signal;

a data detector, wherein the data detector receives the filtered output and performs a data detection on the filtered output to create a detected output;

a first summation element, wherein the first summation element subtracts the filtered output from the detected output to create an error signal;

a second summation element, wherein the second summation element subtracts the error signal from the filtered output to create a wander basis signal; and

a baseline correction feedback circuit, wherein the baseline correction circuit receives the wander basis signal and provides a wander compensation signal, and wherein a derivative of the wander compensation signal is provided as feedback to the digital filter.

20. The data storage device of claim 19 , wherein the baseline correction feedback circuit is a low pass filter, wherein the digital filter is a finite impulse response filter governed by at least one tap, and wherein the data storage device further includes:

an accumulator circuit, wherein the accumulator circuit accumulates a plurality of the error signal, and wherein the accumulator circuit provides an accumulation signal;

a third summation element, wherein the third summation element aggregates the wander compensation signal with the accumulation signal to create the derivative of the wander compensation signal; and

wherein the derivative of the wander compensation signal controls the at least one tap of the digital finite impulse response filter.

Assignments (11)