Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit
View Patent ↗The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104 . An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104 and acquires an arithmetic operation parameter while accessing the arithmetic operation parameter storage unit 105 to determine a width W of the interconnection based on these values. That is, the width W of the interconnection is made to determine upon multiplying (current i) 1/3 by the arithmetic operation parameter (constant), which current is caused to flow through the interconnection.
1. A semiconductor integrated circuit having a first interconnection of width W 1 through which a current i 1 is caused to flow and a second interconnection of width W 2 through which a current i 2 is caused to flow, in which said width W 1 of said first interconnection and said width W 2 of said second interconnection satisfy a relationship specified by the following equation:
W
1
W
2
=
(
i
1
i
2
)
1
3
.
2. The semiconductor integrated circuit according to claim 1 , wherein, in one region of the semiconductor integrated circuit, there are provided “n” (“n” is natural number not less than 2) kinds of interconnection, and the interconnection widths W 1 , . . . W n of the interconnection are designed so as to satisfy W k /W k+1 =(i k /i k+1 ) 1/3 (the width of the interconnection through which the current i k is caused to flow is taken to as W k ; and “k” is natural number not less than “1” to not more than “n−1”).
3. The semiconductor integrated circuit according to claim 1 , wherein both said first interconnection and said second interconnection are copper interconnections.
4. A method for designing the semiconductor integrated circuit having a first interconnection of a width W 1 through which a current i 1 is caused to flow and a second interconnection of a width W 2 through which a current i 2 is caused to flow comprising a step determining an interconnection width ratio W 1 /W 2 by following below equation:
W
1
W
2
=
(
i
1
i
2
)
1
3
5. The method for designing the semiconductor integrated circuit according to claim 4 , wherein said semiconductor integrated circuit has “n” (“n” is natural number not less than 2) kinds of interconnections with different interconnection widths in its one region and comprises a step determining the interconnection widths W 1 , . . . W n of the interconnection so as to satisfy W k /W k+1 =(i k /i k+1 ) 1/3 (the width of the interconnection through which the current i k is caused to flow is taken to as W k ; and “k” is natural number not less than “1” to not more than “n−1”).
6. A system for designing a semiconductor integrated circuit having a first interconnection of a width W 1 through which a current i 1 is caused to flow and a second interconnection of a width W 2 through which a current i 2 is caused to flow comprising:
an interconnection information acquisition unit acquiring interconnection information including identification information specifying the interconnection, and a current value caused to flow into said interconnection that is related to said identification information; and
an arithmetic operation unit determining an interconnection width ratio W 1 /W 2 based on the acquired interconnection information upon following below equation:
W
1
W
2
=
(
i
1
i
2
)
1
3