Divider circuits and methods using in-phase and quadrature signals
Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I−) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q−) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.
1. An integrated circuit comprising:
at least one first divider input receiving an in-phase (I+) signal;
at least one second divider input receiving a complement of the in-phase (I−) signal:
at least one third divider input receiving a quadrature (Q+) signal; and
at least one fourth divider input receiving a complement of the quadrature (Q−) signal,
wherein the integrated circuit comprises a divider and wherein the divider is a divide-by-two,
wherein the divider comprises first and second D-type flip flops.
2. The integrated circuit of claim 1 wherein the first and second D-type flip flops each comprise:
a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input, and first and second differential output nodes; and
a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node, a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, and a second frequency control input.
3. The integrated circuit of claim 2 wherein the first frequency control input in the first D-type flip flop receives the quardrature signal, the second frequency control input in the first D-type flip flop receives the in-phase signal, the first frequency control input in the second D-type flip flop receives the complement of the quadrature signal, and the second frequency control input in the second D-type flip flop receives the complement of the in-phase signal.
4. An integrated circuit comprising:
at least one first divider input receiving an in-phase (I+) signal;
at least one second divider input receiving a complement of the in-phase (I−) signal;
at least one third divider input receiving a quadrature (Q+) signal; and
at least one fourth divider input receiving a complement of the quadrature (Q−) signal,
wherein the divider is a divide-by-six,
wherein the divider comprises first, second, third, fourth, fifth, and sixth D-type flip flops.
5. The integrated circuit of claim 4 wherein the first, second, third, fourth, fifth, and sixth D-type flip flops each comprise:
a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input, and first and second differential output nodes; and
a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node, a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, and a second frequency control input.
6. The integrated circuit of claim 5 wherein the first frequency control input in the first, third, and fifth D-type flip flops receive the quadrature signal, the second frequency control input in the first, third, and fifth D-type flip flops receive the in-phase signal, the first frequency control input in the second, fourth, and sixth D-type flip flops receive a first complement of the quadrature signal, and the second frequency control input in the second, fourth, and sixth D-type flip flops receive a first complement of the in-phase signal.
7. An integrated circuit comprising:
at least one first divider input receiving an in-phase (I+) signal;
at least one second divider input receiving a complement of the in-phase (I−) signal;
at least one third divider input receiving a quadrature (Q+) signal;
at least one fourth divider input receiving a complement of the quadrature (Q−) signal; and
a plurality of circuits each comprising:
a differential circuit having a first bias current; and
a cross-coupled circuit having a second bias current,
wherein the first bias current is greater than the second bias current.
8. The integrated circuit of claim 7 wherein the ratio of the first bias current to the second bias current is within a range from 2 to 3.
9. A divider circuit comprising:
two or more differential circuits each having first and second inputs to receive a first differential signal, a first frequency control input, and first and second differential output nodes, wherein the differential circuit has a first bias current; and
two or more cross-coupled circuits each having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node, a second control terminal coupled to a first output of the cross-coupled circuit and the second differential output node, and a second frequency control input, wherein the cross-coupled circuit has a second bias current;
wherein a first frequency control input in a first differential circuit is coupled to a quadrature signal, a second frequency control input in a first cross-coupled circuit is coupled to an in-phase signal, a first frequency control input in a second differential circuit is coupled to a complement of the quadrature signal, and a second frequency control input in a second cross-coupled circuit is coupled to a complement of the in-phase signal.
10. The divider circuit of claim 9 wherein the divider circuit is a divide-by-two.
11. The divider circuit of claim 9 wherein the ratio of the first bias current to the second bias current is within a range from 2 to 3.
12. The method of claim 9 wherein the first bias current is greater than the second bias current.
13. A method of dividing a frequency of a signal comprising:
receiving an in-phase (I+) signal on at least one first input of a divider;
receiving a complement of the in-phase (I−) signal on at least one second input of the divider;
receiving a quadrature (Q+) signal on at least one third input of the divider; and
receiving a complement of the quadrature (Q−) signal on at least one fourth input of the divider,
wherein the quadrature signal is received on a frequency control input of a differential circuit in a first D-type flip flop, the in-phase signal is received on a frequency control input of a cross-coupled circuit in the first D-type flip flop, the complement of the quadrature signal is received on a frequency control input of a differential circuit in a second D-type flip flop, and the complement of the in-phase signal is received on a frequency control input of a cross-coupled circuit in the second D-type flip flop.
14. The method of claim 13 wherein the ratio of a bias current in the differential circuit to a bias current in the cross-coupled circuit is within a range from 2 to 3.
15. The method of claim 13 wherein a bias current in the differential circuit is greater than a bias current in the cross-coupled circuit.
16. A method of dividing a frequency of a signal comprising:
receiving an in-phase (I+) signal on at least one first input of a divider;
receiving a complement of the in-phase (I−) signal on at least one second input of the divider;
receiving a quadrature (Q+) signal on at least one third input of the divider; and
receiving a complement of the quadrature (Q−) signal on at least one fourth input of the divider,
wherein the quadrature signal is received on frequency control inputs of differential circuits in first, third, and fifth D-type flip flops, the in-phase signal is received on frequency control inputs of cross-coupled circuits in the first, third, and fifth D-type flip flops, the complement of the quadrature signal is received on frequency control inputs of differential circuits in second, fourth, and sixth D-type flip flops, and the complement of the in-phase signal is received on frequency control inputs of cross-couple circuits in the second, fourth, and sixth D-type flip flops.
17. The method of claim 16 wherein the ratio of a bias current in the differential circuit to a bias current in the cross-coupled circuit is within a range from 2 to 3.
18. The method of claim 16 wherein a bias current in the differential circuit is greater than a bias current in the cross-coupled circuit.
19. An integrated circuit comprising:
a divider circuit for dividing signal frequencies;
at least one first divider input receiving an in-phase (I+) signal;
at least one second divider input receiving a complement of the in-phase (I−) signal;
at least one third divider input receiving a quadrature (Q+) signal; and
at least one fourth divider input receiving a complement of the quadrature (Q−) signal,
wherein the divider comprises a differential circuit and a cross-coupled circuit, and wherein a bias current in the differential circuit is greater than a bias current in the cross-coupled circuit.
20. A method of dividing a frequency of a signal comprising:
receiving an in-phase (I+) signal on at least one first input of a divider circuit;
receiving a complement of the in-phase (I−) signal on at least one second input of the divider;
receiving a quadrature (Q+) signal on at least one third input of the divider; and
receiving a complement of the quadrature (Q−) signal on at least one fourth input of the divider,
wherein the divider circuit comprises a differential circuit and a cross-coupled circuit, and wherein a bias current in the differential circuit is greater than a bias current in the cross-coupled circuit.