Semiconductor chip and method for manufacturing the same and semiconductor device
View Patent ↗The semiconductor chip 1 has a semiconductor substrate 10 . In the present embodiment, the semiconductor substrate 10 , which is an SOI substrate, is constituted by comprising a support substrate 12 , an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A 1 provided in the silicon layer 16 . An insulating region 18 is provided on the semiconductor substrate 10 . The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A 1.
1. A semiconductor chip comprising:
a semiconductor substrate having a circuit forming region,
wherein said semiconductor substrate has an insulating layer contacting a bottom face of said circuit forming region and a first insulating region surrounding the entire side face of said circuit forming region, and
wherein said semiconductor substrate comprises a metal film contacting said first insulating region and surrounding said first insulating region.
2. The semiconductor chip according to claim 1 , wherein said semiconductor substrate further comprises a second insulating region contacting said metal film and surrounding said metal film.
3. The semiconductor chip according to claim 1 , wherein said semiconductor substrate further comprises a through electrode, which is provided in said circuit forming region and comprising a same metal as said metal film.
4. The semiconductor chip according to claim 1 , wherein said first insulating region comprises an SiN film.
5. The semiconductor chip according to claim 1 , wherein said first insulating region comprises a first silicon oxide film, a silicon nitride film and a second silicon oxide film which are sequentially formed.
6. A semiconductor device which is provided with the semiconductor chip according to claim 1 .
7. The semiconductor device according to claim 1 , wherein said insulating region contacts said insulating layer.