IP Library Granted Patent US 7,334,202
Granted Patent B1
US 7,334,202 · App. 11/145,327 · Granted Feb 19, 2008

Optimizing critical dimension uniformity utilizing a resist bake plate simulator

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Quick Facts
Patent No.
US 7,334,202
App. No.
11/145,327
Granted
Feb 19, 2008
Kind
B1
Abstract

A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

Claims (127)

1. A system for optimizing critical dimension uniformity in semiconductor manufacturing processes, comprising:

a bake plate simulator that includes a thermal model of a bake plate;

a finite element analysis engine that accesses data from the thermal model and calculates a heat diffusion equation wherein the heat diffusion equation differentiates temperature with respect to at least two spatial coordinates of a zone; and

a lithography simulator that uses calculation results from the finite element analysis engine to derive predicted results of a lithographic process.

2. The system of claim 1 , wherein the thermal model is a model of a multi-zone bake plate.

3. The system of claim 2 , wherein the heat diffusion equation is a two-dimensional steady state heat diffusion equation.

4. The system of claim 3 , wherein the heat diffusion equation is:

x

(

k

T

x

)

+

y

(

k

T

y

)

+

S

i

-

h

i

(

T

-

T

a

)

=

0

where k is thermal conductivity, T is temperature, S i is heating power of an i th zone of a plurality of zones, h i is an effective convection coefficient of the i th zone, and T a is the ambient temperature.

5. The system of claim 1 , further comprising a controller that adjusts a lithography process based at least in part upon predicted results from the lithography simulator.

6. The system of claim 5 , further comprising a graphical user interface that accepts user input for system components.

7. The system of claim 6 , wherein the graphical user interface includes graphical representations of critical dimension information.

8. The system of claim 7 , wherein the graphical user interface includes contour map representations and altitude map representations of temperature information in graphical depictions.

9. The system of claim 6 , wherein the graphical user interface includes contour map representations and altitude map representations of temperature information in graphical depictions.

10. A system for optimizing critical dimension uniformity in semiconductor manufacturing processes, comprising:

a module configured to accept user input in the form of bake plate settings;

a memory containing critical dimension metrology data and post-exposure bake temperature data therein; and

a simulation engine that uses a bake plate simulator, a finite element analysis that calculates a heat diffusion equation wherein the heat diffusion equation differentiates temperature with respect to at least two spatial coordinates of a zone, and a lithography simulator to calculate a post-exposure temperature distribution and a critical dimension distribution.

11. The system of claim 10 , wherein the lithography simulator is a data library.

12. The system of claim 11 , wherein the data library is a data storeselected from the group consisting of a relational database, an object-oriented database, a data definition file, an extensible markup language file, and a text file.

13. The system of claim 10 , wherein the finite element analysis engine calculates a solution for a two-dimensional heat diffusion equation.

14. The system of claim 13 , wherein the two-dimensional heat diffusion equation is:

x

(

k

T

x

)

+

y

(

k

T

y

)

+

S

i

-

h

i

(

T

-

T

a

)

=

0

where k is thermal conductivity, T is temperature, S i is heating power of an i th zone of a plurality of zones, h i is an effective convection coefficient of the i th zone, and T a is the ambient temperature.

15. The system of claim 10 , further comprising a tuning module for adjusting parameters of the bake plate simulator.

16. A method for predicting post-exposure bake results in a semiconductor manufacturing process, comprising:

simulating parameters of a bake plate;

using the simulated parameters to calculate missing parameters in a heat diffusion equation wherein the heat diffusion equation differentiates temperature with respect to at least two spatial coordinates of a zone; and

using the simulated parameters and calculated parameters to predict a resulting critical dimension distribution.

17. The method of claim 16 , further comprising:

calibrating simulated parameters based upon bake plate measurements.

18. The method of claim 17 , further comprising:

using the critical dimension distribution to calculate a post-exposure bake temperature distribution.

19. The method of claim 18 , further comprising:

using the post-exposure bake temperature distribution to adjust bake plate settings.

20. The method of claim 16 , further comprising:

creating a graphical representation of the critical dimension distribution.

21. A system for predicting post-exposure bake results in a semiconductor manufacturing process, comprising:

means for simulating parameters of a bake plate;

means for using the simulated parameters to calculate missing parameters in a heat diffusion equation wherein the heat diffusion equation differentiates temperature with respect to at least two spatial coordinates of a zone; and

means for using the simulated parameters and calculated parameters, to predict a resulting critical dimension distribution.

22. The system of claim 21 , further comprising:

means for calibrating simulated parameters based upon bake plate measurements.

23. The system of claim 22 , further comprising:

means for using the critical dimension distribution to calculate a post-exposure bake temperature distribution.

24. The system of claim 23 , further comprising:

means for using the post-exposure bake temperature distribution to adjust bake plate settings.

25. The system of claim 21 , further comprising:

means for creating a graphical representation of the critical dimension distribution.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2020
From: ADVANCED MICRO DEVICES, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 051861/0682 →