Patent Assignment
Reel/Frame 051861/0682
Assignment of Assignor's Interest
Recorded: 2020-02-19
Pages: 9
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2019-12-24
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Properties
(40)
Method and Apparatus for Process Control of Alignment in Dual Damascene Processes
Patent:
6,486,036 →
Application:
09/606,135 →
Method and Apparatus for Reducing Deposition Variation by Modeling Post-Clean Chamber Performance
Patent:
6,512,991 →
Application:
09/614,312 →
Reverse Mask and Oxide Layer Deposition for Reduction of Vertical Capacitance Variation in Multi-Layer Metallization Systems
Patent:
6,660,618 →
Application:
09/640,080 →
Method of Controlling Photoresist Thickness Based Upon Photoresist Viscosity
Patent:
6,524,774 →
Application:
09/650,545 →
Method of Copper-Polysilicon Gate Formation
Patent:
6,440,830 →
Application:
09/651,760 →
Forming and filling a recess in interconnect with alloy to minimize electromigration
Patent:
6,358,840 →
Application:
09/655,699 →
BC13/Ar Chemistry for Metal Overetching on a High Density Plasma Etcher
Patent:
6,387,820 →
Application:
09/664,950 →
Plating System with Shielded Secondary Anode for Semiconductor Manufacturing
Patent:
6,402,909 →
Application:
09/678,504 →
Coherent Alloy Diffusion Barrier for Integrated Circuit Interconnects
Patent:
6,462,417 →
Application:
09/772,750 →
Automated Method of Controlling Photoresist Develop Time to Control Critical Dimensions, and System for Accomplishing Same
Patent:
6,569,692 →
Application:
09/776,087 →
Method of Making a Slot via Filled Dual Damascene Structure with Middle Stop Layer
Patent:
6,365,505 →
Application:
09/780,531 →
Formation of confined halo regions in field effect transistor
Patent:
6,297,117 →
Application:
09/781,389 →
Method of Making a Slot via Filled Dual Damascene Structure with a Middle Stop Layer
Patent:
6,444,573 →
Application:
09/788,472 →
Method of Making a Slot via Filled Dual Damascene Structure with Middle Stop Layer
Patent:
6,391,766 →
Application:
09/788,641 →
Method of Fabricating a Semiconductor Device Having a Metal Oxide High-K Gate Insulator by Localized Laser Irradiation and a Device Thereby Formed
Patent:
6,531,368 →
Application:
09/825,750 →
Method of Identifying Film Stacks Based Upon Optical Properties
Patent:
6,618,149 →
Application:
09/827,534 →
Semiconductor Wafer Polishing Apparatus
Patent:
6,462,409 →
Application:
09/876,259 →
Closed Loop Residual Gas Analyzer Process Control Technique
Patent:
6,955,928 →
Application:
09/883,883 →
Process for Forming a Photoresist Mask
Patent:
6,689,541 →
Application:
09/884,182 →
Integrated Circuit Manufacturing Method Including Seed Layer Deposition, Removal, and Subsequent Deposition
Patent:
6,455,413 →
Application:
09/894,525 →
Multilayer Anti-Reflective Coating for Semiconductor Lithography
Patent:
6,689,682 →
Application:
09/924,670 →
Method and Apparatus for Controlling a Stepper
Method of Forming an Epitaxial Layer for Raised Drain and Source Regions by Removing Surface Defects of the Initial Crystal Surface
Optimizing Critical Dimension Uniformity Utilizing a Resist Bake Plate Simulator
Patent:
7,334,202 →
Application:
11/145,327 →
Method of Forming Sidewall Spacers
Method and Apparatus for Classifying Faults Based on Wafer State Data and Sensor Tool Trace Data
Patent:
7,277,824 →
Application:
11/180,393 →
Method and Apparatus for Dynamic Adjustment of Sensor and/or Metrology Sensitivities
Patent:
7,502,702 →
Application:
11/221,078 →
Technique for Forming a Transistor Having Raised Drain and Source Regions with a Tri-Layer Hard Mask for Gate Patterning
A Semiconductor Device Comprising a Copper Alloy as a Barrier Layer in a Copper Metallization Layer
Method for Removing a Passivation Layer Prior to Depositing a Barrier Layer in a Copper Metallization Layer
Gate Straining in a Semiconductor Device
Method of Testing an Integrity of a Material Layer in a Semiconductor Structure
Method of Forming Transistor Devices with Different Threshold Voltages Using Halo Implant Shadowing
High Yield Plasma Etch Process for Interlayer Dielectrics
Method of Forming a Metal Directly on a Conductive Barrier Layer by Electrochemical Deposition Using an Oxygen-Depleted Ambient
Method and System for Controlling Transport Sequencing in a Process Tool by a Look-Ahead Mode
Drive Current Adjustment for Transistors by Local Gate Engineering
Reducing Metal Voids in a Metallization Layer Stack of a Semiconductor Device by Providing a Dielectric Barrier Layer
Technique for Compensating for a Difference in Deposition Behavior in an Interlayer Dielectric Material
Sidewall Graphene Devices for 3-D Electronics