Method of testing an integrity of a material layer in a semiconductor structure

1. A method, comprising:

providing a semiconductor structure, said semiconductor structure comprising a feature comprising a first material, a dielectric layer formed over said feature, and a layer comprising a second material formed over said feature, wherein said dielectric layer comprises a contact via formed therein, said contact via being located over said feature;

filling said contact via with said first material;

after filling said contact via with said first material, exposing said semiconductor structure to an etchant, said etchant being adapted to selectively remove said first material relative to said second material; and

after exposing said semiconductor structure to said etchant, detecting whether said feature has been etched by said etchant.

2. The method of claim 1 , wherein said etchant is adapted to leave said second material substantially intact.

3. The method of claim 1 , wherein said first material comprises a metal.

4. The method of claim 3 , wherein said metal comprises copper.

5. The method of claim 1 , wherein said second material comprises at least one of titanium, tantalum, titanium nitride and tantalum nitride.

6. The method of claim 1 , wherein said layer comprising said second material is formed over at least a bottom surface of said contact via.

7. The method of claim 1 , wherein said feature comprises a trench filled with said first material.

8. The method of claim 1 , further comprising forming a trench in said dielectric layer, said trench being located over said feature.

9. The method of claim 8 , further comprising filling said contact via and said trench with said first material prior to exposing said semiconductor structure to said etchant.

10. The method of claim 1 , wherein exposing said semiconductor structure to said etchant comprises performing a wet etch process.

11. The method of claim 10 , wherein said etchant comprises at least one of ammoniumperoxidisulfate and iron(III)-chloride.

12. The method of claim 1 , wherein detecting whether said feature has been etched by said etchant comprises performing at least one of electron microscopy and optical microscopy.

13. The method of claim 1 , further comprising dissecting said semiconductor structure prior to detecting whether said feature has been etched by said etchant.

14. The method of claim 1 , further comprising performing a chemical mechanical polishing process prior to detecting whether said feature has been affected by said etchant.

15. A method, comprising:

providing a semiconductor structure, said semiconductor structure comprising:

a substrate;

an electrically conductive feature formed in said substrate, said electrically conductive feature comprising a first material;

a dielectric layer formed over said substrate;

a contact via formed in said dielectric layer; and

a barrier layer formed over at least a portion of said feature at a bottom of said contact via, said barrier layer comprising a second material;

forming a layer comprising said first material over said barrier layer;

after forming said layer comprising said first material over said barrier layer, exposing said semiconductor structure to an etchant, said etchant being adapted to selectively remove said first material relative to said second material; and

after exposing said semiconductor structure to said etchant, detecting whether said feature has been etched by said etchant.

16. The method of claim 15 , further comprising performing a planarization process adapted to remove portions of said layer of said first material prior to exposing said semiconductor structure to said etchant.

17. The method of claim 15 , wherein said detecting whether said feature has been etched by said etchant comprises performing at least one of scanning electron microscopy and optical microscopy.

18. The method of claim 15 , wherein said semiconductor structure comprises a plurality of contact vias, and wherein said electrically conductive feature and said layer of said first material are adapted to electrically connect at least two of said contact vias in series.