Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer
View Patent ↗Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as isolated copper voids and the like may be reduced without significantly affecting overall performance of the metallization system.
1. A method, comprising:
forming an opening having an initial lateral size in a low-k dielectric layer of a metallization layer formed above a substrate of a semiconductor device;
after forming said opening, performing an etch process to increase said initial lateral size of said opening;
after increasing said initial lateral size of said opening, forming a dielectric layer in said opening with a thickness that substantially re-establishes said initial lateral size of said opening, said dielectric layer having a higher density relative to said low-k dielectric layer;
exposing a conductive material of a conductive region at a bottom of said opening by removing material of said dielectric layer;
depositing a conductive barrier material in said opening; and
filling said opening with a metal.
2. The method of claim 1 , wherein said dielectric layer comprises silicon dioxide.
3. The method of claim 1 , wherein filling said opening with said metal comprises forming a metal layer by an electrochemical deposition technique.
4. The method of claim 1 , further comprising forming a seed layer on said conductive barrier layer.
5. The method of claim 1 , wherein forming said dielectric layer comprises forming a first dielectric layer on exposed sidewall surfaces of said opening and forming a second dielectric layer on said first dielectric layer.
6. The method of claim 5 , wherein at least one of said first and second dielectric layers comprises nitrogen.
7. The method of claim 1 , wherein said dielectric layer comprises a dielectric material having a diffusion hindering effect with respect to an atomic species of said metal.
8. The method of claim 7 , wherein said dielectric material of said dielectric layer comprises nitrogen.
9. The method of claim 7 , wherein said conductive barrier material is deposited so as to have a thickness of approximately 30 nm or less at horizontal surface areas outside of said opening.
10. A method, comprising:
forming an opening in a low-k dielectric material of a metallization layer of a semiconductor device;
after forming said opening, performing an isotropic etch process so as to remove a portion of said low-k dielectric material within said opening;
after performing said isotropic etch process, depositing a layer of low-k dielectric material;
after depositing said layer of low-k dielectric material, forming a silicon dioxide material above exposed surfaces of said opening;
removing said silicon dioxide material at a bottom of said opening, while maintaining at least a portion of said silicon dioxide material at sidewalls of said opening; and
filling said opening with a metal-containing conductive material.
11. The method of claim 10 , further comprising depositing a conductive barrier material in said opening after removing said silicon dioxide material from the bottom of said opening.
12. The method of claim 11 , further comprising forming a seed layer on said conductive barrier material.
13. The method of claim 10 , further comprising forming a dielectric barrier material above said surfaces of said opening.
14. The method of claim 13 , wherein said dielectric barrier material is formed on said surfaces.