Nonvolatile semiconductor memory
A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
1. A nonvolatile semiconductor memory comprising:
a bit line;
a source line being perpendicular to the bit line;
a memory cell unit array including a first memory cell unit and a second memory cell unit connected to the first memory cell unit in series along to the bit line, the first memory cell unit including first and second select gate transistors and a plurality of memory cell transistors arranged between the first and second select gate transistors in series, the second memory cell unit including third and fourth select gate transistors and a plurality of memory cell transistors arranged between the third and fourth select gate transistors in series, the second select gate transistor of the first memory cell unit connected to the third select gate transistor of the second memory cell unit via an inter-unit diffusion layer, a length of the first memory cell unit being equal to a length of the second memory cell unit;
a bit line contact connecting the first select gate transistor of the first memory cell and the bit line; and
a source line contact connecting the fourth select gate transistor of the second memory cell unit and the source line;
wherein, the memory cell unit array is located having a shift length equal to the integral multiple length of the memory cell units aligned in a bit line direction so as to be staggered from each other as compared with adjacent memory cell unit arrays aligned in a source line direction.
2. The nonvolatile semiconductor memory of claim 1 ,
wherein each memory cell transistor includes a charge storage portion and a control gate applying a voltage to the charge storage portion, when selecting one of the first and the second memory cell units a single memory cell transistor from the selected memory cell unit so as to perform read-out, a positive voltage is applied to control gates of memory cell transistors in unselected memory cell units other than the selected memory cell unit.
3. The nonvolatile semiconductor memory of claim 1 ,
wherein each memory cell transistor includes a charge storage portion and a control gate applying a voltage to the charge storage portion, when selecting one of the first and the second memory cell units and a single memory cell transistor from the selected memory cell unit so as to perform write-in, a positive voltage is applied to control gates of memory cell transistors in unselected memory cell units other than the selected memory cell unit.