Word line driving circuit with a word line detection circuit

1. A semiconductor storage device comprising:

a word line driving circuit adapted for driving a word line by a driving potential changed in stages upon rise or fall, wherein

the word line driving circuit comprises a detection circuit for detecting the signal level of the word line to output the result of detection, with a timing of said word line driving potential being controlled based on an output of said detection circuit that said word line has been driven toward a second potential.

2. The semiconductor storage device as defined in claim 1 wherein said word line driving circuit drives said word line from a first potential towards the second potential;

said detection circuit detects that said word line has been driven towards said second potential; and wherein

said word line is driven towards a third potential based on an output of said detection circuit that said word line has been driven toward the second potential.

3. The semiconductor storage device as defined in claim 2 wherein said second potential is somewhere between said first and third potentials.

4. The semiconductor storage device as defined in claim 2 wherein said first potential is higher than a power supply voltage of said word line driving circuit, said second potential is the ground potential of said word line driving circuit, and wherein said third potential is lower than said ground potential.

5. The semiconductor storage device as defined in claim 2 wherein said first potential is lower than the ground potential of said word line driving circuit, said second potential is the potential of a power supply voltage of said word line driving circuit, and wherein said third potential is higher than said power supply voltage.

6. The semiconductor storage device as defined in claim 1 wherein said semiconductor storage device is a DRAM.

7. A semiconductor storage device comprising

a first driving circuit for driving a word line towards a first potential;

a second driving circuit for driving said word line towards a second potential;

a third driving circuit for driving said word line towards a third potential; and

a driving control circuit for actuating said first driving circuit when an input signal is at a first logical value, for actuating said second driving circuit when said input signal transfers from the first logical value to a second logical value and for actuating said third driving circuit on detection that said word line has been driven towards the second potential.

8. The semiconductor storage device as defined in claim 7 wherein said second potential is somewhere between said first and third potentials.

9. The semiconductor storage device as defined in claim 7 wherein said first potential is higher than a power supply voltage of said driving control circuit, said second potential is the ground potential of said driving control circuit, and wherein said third potential is lower than said ground potential.

10. The semiconductor storage device as defined in claim 7 wherein said first potential is lower than the ground potential of said driving control circuit, said second potential is the potential of a power supply voltage of said driving control circuit, and wherein said third potential is higher than said power supply voltage.

11. The semiconductor storage device as defined in claim 7 wherein said driving control circuit includes a logical circuit for detecting that said word line has been driven towards said second potential, and wherein said logical circuit is driven by a power supply voltage of said driving control circuit.

12. The semiconductor storage device as defined in claim 7 wherein said first and third driving circuits include a circuit for converting the signal level of said input signal.

13. The semiconductor storage device as defined in claim 7 wherein said semiconductor storage device is a DRAM.

14. A semiconductor storage device comprising:

a first driving circuit for driving a word line towards a first potential;

a second driving circuit for driving said word line towards a second potential;

a third driving circuit for driving said word line towards a third potential;

a fourth driving circuit for driving said word line towards a fourth potential; and

a driving control circuit for actuating the first driving circuit when an input signal is at a first logical value, for actuating the second driving circuit when said input signal transfers from said first logical value to a second logical value, for actuating the third driving circuit on detection that said word line has been driven towards said second potential, for actuating the fourth driving circuit when said input signal transfers from said second logical value towards said first logical value, and for actuating the first driving circuit on detection that said word line has been driven towards said fourth potential.

15. The semiconductor storage device as defined in claim 14 wherein said first potential is lower than the ground potential of said driving control circuit, said second potential is the potential of a power supply voltage of said driving control circuit, said third potential is higher than said power supply voltage and wherein said fourth potential is the ground potential of said driving control circuit.

16. The semiconductor storage device as defined in claim 14 wherein said driving control circuit includes a first logical circuit for detecting that said word line has been driven towards said second potential and a second logical circuit for detecting that said word line has been driven towards said fourth potential, said first and second logical circuits operating at a power supply voltage of said driving control circuit.

17. The semiconductor storage device as defined in claim 14 wherein said first and third driving circuits include a circuit for converting the signal level of said input signal.

18. The semiconductor storage device as defined in claim 14 wherein said semiconductor storage device is a DRAM.