Top layers of metal for high performance IC's
View Patent ↗A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1. A method for fabricating an integrated circuit chip, comprising:
providing a silicon substrate, multiple devices in and on said silicon substrate,
a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;
forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises forming a photosensitive polymer layer on said passivation layer;
after said forming said polymer layer, forming an opening through said polymer layer and through said passivation layer to expose a contact point of said first metallization structure; and
forming a second metallization structure over said contact point, in said opening and on said polymer layer, wherein said second metallization structure comprises a first portion and a second portion over said first portion and over said polymer layer, wherein said first portion is formed by a first process comprising a sputtering process, and said second portion is formed by a second process comprising a copper electroplating process.
2. The method of claim 1 , wherein said forming said photosensitive polymer layer comprises forming a photosensitive polyimide layer on said passivation layer.
3. The method of claim 1 further comprising curing said polymer layer.
4. The method of claim 1 further comprising curing said polymer layer in a nitrogen ambient.
5. The method of claim 1 further comprising curing said polymer layer at a temperature between 250 and 450 degrees C.
6. The method of claim 1 further comprising curing said polymer layer for a time between 0.5 and 1.5 hours.
7. The method of claim 3 , wherein after said curing said polymer layer, said polymer layer has a thickness between 2 and 30 micrometers.
8. The method of claim 1 further comprising curing said polymer layer in a vacuum ambient.
9. The method of claim 1 , wherein said nitride layer has a thickness between 0.5 and 2 micrometers.
10. The method of claim 1 , wherein said first process comprises an aluminum sputtering process.
11. The method of claim 1 , wherein said second metallization structure further comprises a solder over said second portion.
12. The method of claim 1 , wherein said second metallization structure further comprises a metal pad used to be connected with a wirebonding interconnect.
13. The method of claim 1 , wherein said passivation layer further comprises an oxide layer under said nitride layer.
14. The method of claim 1 , wherein said nitride layer is the topmost nitride layer of said integrated circuit chip.
15. The method of claim 1 , wherein said second metallization structure further comprises a metal bump over said second portion.
16. The method of claim 1 , wherein said first metallization structure comprises a topmost sub-micron integrated circuit of said integrated circuit chip.
17. The method of claim 1 , wherein said second metallization structure comprises a tens-micron interconnecting metallization.