High-speed internal bus architecture for an integrated circuit
View Patent ↗An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.
1. An internal bus architecture for modules in an integrated circuit (IC), said internal bus architecture comprising:
at least two source interface units and at least two destination interface units for interfacing with the modules of said IC; and
at least one basic modular unit coupled to said source interface units and to said destination interface units, the at least one basic modular unit comprising an upload unit for transferring upstream data; and a download unit for transferring downstream data;
the upload unit and the download unit in each of said basic modular units being mutually independent and being adapted under control of a transaction protocol to simultaneously transfer upstream data and downstream data;
the upload unit comprising a buffer having a pair of internal-buffers for temporary storage of data to be transferred from the source interface unit to the destination interface unit, wherein data from either internal buffer can be transferred in a single clock cycle.
2. The internal bus architecture of claim 1 , wherein said upload unit comprises:
an input multiplexer (MUX) connected to the source interface units;
an arbiter for selecting a single input of said input MUX to enable only a single source interface unit to transfer data to the destination interface unit;
an output MUX coupled to said buffer and said destination interface unit; and
a controller for controlling reading and writing of data to and from said buffer.
3. The internal bus architecture of claim 2 , wherein arbitration between the source interface units is performed if the source interface units request to transfer data to the destination interface unit in the same clock cycle.
4. The internal bus architecture of claim 3 , wherein said arbitration is performed according to a predefined arbitration mode of said arbiter.
5. The internal bus architecture of claim 4 , wherein said arbitration mode includes any one of: a prioritized mode, a round robin mode, a weighted round robin mode.
6. The internal bus architecture of claim 2 , wherein said controller alternately writes data to respective ones of said internal-buffers during each successive clock cycle.
7. The internal bus architecture of claim 6 , wherein said controller alternately reads data from respective ones of said internal-buffers by enabling a single input of said output MUX.
8. The internal bus architecture of claim 7 , wherein alternation is performed in each clock cycle.
9. The internal bus architecture of claim 1 , wherein said download unit comprises at least:
an input multiplexer (MUX) connected to the source interface units;
an arbiter for selecting a single input of said input MUX to enable only a single source interface unit to transfer data to the destination interface unit;
an output MUX coupled to said buffer and said destination interface unit; and
a controller for controlling reading and writing of data to and from said buffer; and
wherein the buffer in the download unit has a pair of internal-buffers for temporary storage of data to be transferred from the source interface units to the destination interface unit, wherein data from either internal buffer can be transferred in a single clock cycle.
10. The internal bus architecture of claim 9 , wherein the arbitration between the source interface units is performed if said source interface units request to transfer data to the destination interface unit at the same time.
11. The internal bus architecture of claim 10 , wherein said arbitration is performed according to a predefined arbitration mode of said arbiter.
12. The internal bus architecture of claim 11 , wherein said arbitration mode includes any one of: a prioritized mode, a round robin mode, a weighted round robin mode.
13. The internal bus architecture of claim 9 , wherein said controller alternately writes data to respective ones of said internal-buffers.
14. The internal bus architecture of claim 13 , wherein said controller alternately reads data from respective ones of said internal-buffers by enabling a single input of said output MUX.
15. The internal bus architecture of claim 14 , wherein alternation is performed in each clock cycle.
16. The internal bus architecture of claim 1 , wherein each of the modules of said IC comprises at least one in the group of: a peripheral unit, a basic modular unit, a configurable interfaces, a processor.
17. The internal bus architecture of claim 1 , having at least two basic modular units connected to each other to form a bus topology.
18. The internal bus architecture of claim 17 , wherein said bus topology includes at least one of: a tree topology, a matrix topology, a ring topology, or any combination thereof.
19. The internal bus architecture of claim 1 , wherein the integrated circuit is an application specific integrated circuit (ASIC).
20. A method for high-speed inter-communicating between modules connected in an integrated circuit (IC) via an internal bus architecture comprising:
at least two source interface units and at least two destination interface units for interfacing with the modules of said IC; and
at least one basic modular unit coupled to said source interface units and to said destination interface units and comprising an upload unit for transferring upstream data; and a download unit for transferring downstream data;
the method comprising:
temporarily storing said upstream data in a buffer of a pair of internal buffers of the upload unit;
temporarily storing said downstream data in a buffer of a pair of internal buffers of the download unit;
simultaneously sampling the upstream data and the downstream data from the respective buffers; and
simultaneously transferring the upstream data to a first one of the destination units and the downstream data to a second one of the destination units, wherein data from either buffer of the internal buffers can be transferred in a single clock cycle.
21. The method of claim 20 , further including:
arbitrating between the source interface units for transferring data to the destination interface unit from only a single one of the source interface units;
temporarily storing data to be transferred from the source interface units to the destination interface unit in one of the pair of internal-buffers of one of said upload unit buffer or said download unit buffer; and
controlling reads and writes of said data to and from said internal-buffers.
22. The method of claim 21 , wherein arbitrating between the source interface units is performed if said source interface units request to transfer a data item to the destination interface unit in the same clock cycle.
23. The method of claim 21 , wherein controlling writes of said data further comprises:
alternately writing data, in each clock cycle, between respective ones of said internal-buffers.
24. The method of claim 21 , wherein controlling reads of said data further comprises enabling, in each clock cycle, a different one of said internal buffers.
25. The method of claim 20 , including controlling said basic modular unit by means of a transaction protocol that allows the data to be transferred simultaneously using a request (REQ) signal and acknowledge (ACK) signal.
26. The method of claim 25 , wherein said REQ signal is asserted by the source interface unit once said source interface unit is ready to transfer data.
27. The method of claim 25 , wherein said ACK signal is asserted by the destination interface unit once said destination interface unit is ready to receive data.
28. The method of claim 20 , further comprising connecting at least two of said basic modular units to each other to form a bus topology.
29. The method of claim 28 , wherein said bus topology includes at least one of: a tree topology, a matrix topology, a ring topology, or any combination thereof.
30. The method of claim 20 , wherein the integrated circuit is an application specific integrated circuit (ASIC).