This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.
1. A method of fabricating a memory device, comprising:
providing a substrate;
forming an access transistor on said substrate, said access transistor having a first and a second active area;
providing a bit line in electrical contact with said access transistor at said first active area;
providing an interconnect in electrical contact with said access transistor at said second active area, wherein said interconnect is oriented substantially vertically with respect to said substrate; and
forming a plurality of variable resistance memory cells in a substantially vertical arrangement with respect to said substrate, wherein in said substantially vertical arrangement the plurality of variable resistance memory cells are positioned substantially one above another and each of said variable resistance memory cells in said substantially vertical arrangement is defined at a respective intersection of a respective sense line and a respective common line, with each of said respective sense lines being associated with a single respective said variable resistance memory cell and in electrical communication with said interconnect.
2. The method of claim 1 , where each respective act of forming said plurality of variable resistance memory cells comprises:
forming one of said respective sense lines;
forming a memory storage region over said respective sense line; and
providing a respective common line over said memory storage region.
3. The method of claim 2 , where said respective common line is formed orthogonal to said respective sense line.
4. The method of claim 2 , where said respective common line is formed orthogonal to a respective write-only line.
5. The method of claim 2 , further comprising providing a sense amplifier in electrical contact with said bit line.
6. The method of claim 1 , where said forming said access transistor comprises:
forming source and drain regions and a gate structure between said source and drain regions; and
providing conductive plugs to said source and drain regions, said bit line being in electrical contact with one of said conductive plugs and said interconnect being in electrical contact with the other of said conductive plugs.
7. The method of claim 6 , wherein said plurality of variable resistance memory cells comprise at least three memory cells.
8. The method of claim 1 , wherein said first memory bit is an MRAM memory element.
9. The method of claim 1 , wherein said first memory bit is a PCRAM memory element.
10. The method of claim 1 , wherein said first memory bit is an FERAM memory element.
11. The method of claim 1 , wherein said first memory bit is a polymer memory element.
12. The method of claim 1 , wherein said first memory bit is a phase-changing chalcogenide memory element.
13. A method of forming a memory device, comprising:
providing a sense amplifier;
providing an interconnect;
providing an access transistor capable of electrically connecting said sense amplifier and said interconnect;
providing n array planes over said access transistor, each of said n array planes comprising at least one memory cell, said at least one memory cell comprising a common line, wherein n is equal to 2 or greater; and
providing a plurality of sense lines, each associated with a respective said at least one memory cell of said n array planes and being in electrical contact with said interconnect.
14. A method of reading memory stored in a memory cell, comprising:
selecting a common line associated with a respective memory bit of a plurality of memory bits, wherein each one of said plurality of memory bits is in a respective plane of memory bits and is associated with a respective sense line;
selecting a wordline of an access transistor, said access transistor being electrically coupled to each said respective sense line by an interconnect to all respective sense lines; and
sensing a memory state of said respective memory bit associated with said common line at a bit line coupled to said access transistor.
15. The method of claim 14 , wherein said respective memory bit of said plurality of memory bits has a read address consisting of an X, Y, and Z coordinate, where X, Y and Z are axes in three dimensions.
16. The method of claim 15 , wherein said selecting a bit line designates one of said X, Y, and Z coordinates of said address of said respective memory bit.
17. The method of claim 16 , wherein said selecting a wordline designates another of said X, Y, and Z coordinates.
18. The method of claim 17 , wherein said selecting a common line designates a third one of said X, Y, and Z coordinates.
19. The method of claim 14 , wherein said plurality of bits are MRAM cells.
20. The method of claim 14 , wherein said plurality of bits are PCRAM cells.
21. The method of claim 14 , wherein said plurality of bits are FERAM cells.
22. The method of claim 14 , wherein said plurality of bits are polymer memory cells.
23. The method of claim 12 , wherein said plurality of bits are phase-changing chalcogenide memory cells.