Bit line reference circuits for binary and multiple-bit-per-cell memories
View Patent ↗Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.
1. A memory comprising:
a bit line connected to a column of memory cells;
a first reference bit line connected to a column of reference cells;
a plurality of word lines, wherein each word line is coupled to control one of the memory cells and one of the reference cells;
a sense amplifier coupled to sense a difference between the bit line and the first reference bit line;
a bias bit line coupled to a column of reference cells, each reference cell coupled to the bias bit line being connected to a corresponding one of the word lines;
a first pull-up device coupled to the first reference bit line during a sensing operation;
a bias pull-up device coupled to the bias bit line during the sensing operation; and
a normal pull-up device coupled to the bit line during the sensing operation, wherein the first and normal pull-up devices are coupled to mirror a current through the bias pull-up device,
wherein the first pull-up device has a first effective size, and the normal pull-up device has an effective size that differs from the first effective size.
2. The memory of claim 1 , wherein the first effective size is about one half of the effective size of the normal pull-up device.
3. The memory of claim 1 , wherein the bias pull-up device has an effective size that is the same as the effective size of the normal pull-up device.
4. A memory comprising:
a bit line connected to a column of memory cells;
a first reference bit line connected to a column of reference cells;
a plurality of word lines, wherein each word line is coupled to control one of the memory cells and one of the reference cells;
a sense amplifier coupled to sense a difference between the bit line and the first reference bit line;
a bias bit line coupled to a column of reference cells, each reference cell coupled to the bias bit line being connected to a corresponding one of the word lines;
a first pull-up device coupled to the first reference bit line during a sensing operation;
a bias pull-up device coupled to the bias bit line during the sensing operation; and
a normal pull-up device coupled to the bit line during the sensing operation, wherein the first and normal pull-up devices are coupled to mirror a current through the bias pull-up device;
a second reference bit line coupled to a second column of reference cells, each reference cell in the second column being connected to a corresponding one of the word lines; and
a second pull-up device coupled to the second reference bit line, wherein the second pull-up device is coupled to mirror the current through the bias pull-up device.
5. The memory device of claim 4 , wherein the main pull-up device has an effective size that differs from an effective size of the first pull-up device and from an effective size of the second pull-up device.
6. The memory of claim 5 , wherein:
each of the memory cells stores a multi-bit value represented by the memory cell having one of a plurality of threshold voltage states; and
the reference cells in the first column are programmed to a first of the threshold voltage states.
7. The memory of claim 6 , wherein:
the reference cells in the second column are programmed to the first of the threshold voltage states; and
the effective size of the first pull-up device differs from the effective size of the second pull-up device.
8. The memory of claim 7 , wherein the effective size of the first pull-up device is smaller that the effective size of the normal pull-up device, and the effective size of the second pull-up device is larger than the effective size of the normal pull-up device.
9. The memory of claim 6 , wherein the reference cells in the second column are programmed to a second of the threshold voltage states.
10. The memory of claim 9 , wherein the effective size of the first pull-up device matches the effective size of the second pull-up device.
11. A multi-bit-per-cell memory comprising:
a bit line coupled to a column of memory cells;
a plurality of reference bit lines, each reference bit line being connected to a column of reference cells;
a plurality of sense amplifiers, wherein during a read operation reading a multi-bit value from a selected one of the memory cells coupled to the bit line, each sense amplifier is coupled to sense a difference between the bit line and a corresponding one of the reference bit lines;
a bias bit line coupled to a column of reference cells;
a normal pull-up device coupled to the bit line during the read operation;
a plurality of reference pull-up devices respectively coupled to the plurality of reference bit lines during the read operation; and
a bias pull-up device coupled to the bias bit line during the read operation, wherein the normal pull-up device and the reference pull-up devices are coupled to mirror a current through the bias pull-up device.
12. The memory of claim 11 , wherein all of the reference devices coupled to the reference bit lines are programmed to the same threshold voltage state, and each of the reference pull-up devices has a different size.
13. The memory of claim 11 , wherein:
the reference cells that are coupled to a first of the reference bit lines are programmed to a first threshold voltage state; and
the reference cells that are coupled to a second of the reference bit lines are programmed to a second threshold voltage state.