Semiconductor device
View Patent ↗A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
1. A semiconductor device comprising:
a first memory cell; and
a second memory cell,
wherein each of said first memory cell and said second memory cell includes four N-channel type MIS transistors, and
wherein a threshold voltage of a first MIS transistor of said first memory cell is smaller than that of a first MIS transistor of said second memory cell.
2. The semiconductor device according to claim 1 , further comprising:
an input/output circuit having an MIS transistor; and
a logic circuit having an MIS transistor,
wherein a threshold voltage of said MIS transistor of said input/output circuit is larger than that of said first MIS transistor of said first memory cell, and
wherein a threshold voltage of said MIS transistor of said logic circuit is smaller than that of said first MIS transistor of said second memory cell.
3. The semiconductor device according to claim 1 , further comprising:
an input/output circuit; and
a logic circuit,
wherein a threshold voltage of an MIS transistor in said logic circuit is equal to that of said first MIS transistor of said first memory cell,
wherein a threshold voltage of said MIS transistor in said input/output circuit is larger than that of said first MIS transistor of said second memory cell,
wherein said first memory cell additionally includes two P-channel type MIS transistors,
wherein said second memory cell additionally includes two P-channel type MIS transistors,
wherein the four N-channel type MIS transistors in each of said first memory cell and said second memory cell are arranged such that the gates of a third MIS transistor and a fourth MIS transistor are connected to a wordline,
wherein the gate of said first MIS transistor is connected to said fourth MIS transistor,
wherein the drain of said first MIS transistor is connected to said third MIS transistor,
wherein the gate of a second MIS transistor is connected to said third MIS transistor, and
wherein the drain of said second MIS transistor is connected to said fourth MIS transistor.
4. The semiconductor device according to claim 1 , further comprising:
an additional MIS transistor having a source-drain path between an operating voltage supply point of said first memory cell and a power line,
wherein said additional MIS transistor is controlled so as to be off in a first state and to be on in a second state, and
wherein, before said second state is changed to said first state, information of said first memory cell is stored into said second memory cell.
5. The semiconductor device according to claim 1 ,
wherein a gate-insulating film thickness of said first MIS transistor of said first memory cell is smaller than that of said first MIS transistor of said second memory cell.
6. The semiconductor device according to claim 5 , further comprising:
an input/output circuit having an MIS transistor; and
a logic circuit having an MIS transistor,
wherein a threshold voltage of said MIS transistor of said input/output circuit is larger than that of said first MIS transistor of said first memory cell, and
wherein a threshold voltage of said MIS transistor of said logic circuit is smaller than that of said first MIS transistor of said second memory cell.
7. The semiconductor device according to claim 5 , further comprising:
an input/output circuit; and
a logic circuit,
wherein a threshold voltage of an MIS transistor in said logic circuit is equal to that of said first MIS transistor of said first memory cell,
wherein a threshold voltage of said MIS transistor in said input/output circuit is larger than that of said first MIS transistor of said second memory cell,
wherein said first memory cell additionally includes two P-channel type MIS transistors,
wherein said second memory cell additionally includes two P-channel type MIS transistors,
wherein the four N-channel type MIS transistors in each of said first memory cell and said second memory cell are arranged such that the gates of a third MIS transistor and a fourth MIS transistor are connected to a wordline,
wherein the gate of said first MIS transistor is connected to said fourth MIS transistor,
wherein the drain of said first MIS transistor is connected to said third MIS transistor,
wherein the gate of a second MIS transistor is connected to said third MIS transistor, and
wherein the drain of said second MIS transistor is connected to said fourth MIS transistor.
8. The semiconductor device according to claim 5 , further comprising:
additional MIS transistor having a source-drain path between an operating voltage supply point of said first memory cell and a power line,
wherein said additional MIS transistor is controlled so as to be off in a first state and to be on in a second state, and
wherein, before said second state is changed to said first state, information of said first memory cell is stored into said second memory cell.