Phase change memory cell defined by imprint lithography
A memory cell includes a first electrode, a second electrode, and a phase-change material between the first electrode and the second electrode. A minimum cross-sectional area of a current path between the first electrode and the second electrode is defined by an imprint lithography process.
1 . A memory cell comprising:
a first electrode;
a second electrode; and
a phase-change material between the first electrode and the second electrode,
wherein a minimum cross-sectional area of a current path between the first electrode and the second electrode is defined by an imprint lithography process.
2 . The memory cell of claim 1 , wherein the imprint lithography process comprises a step and flash imprint lithography process.
3 . The memory cell of claim 1 , wherein the imprint lithography process comprises a nanotransfer printing lithography process.
4 . The memory cell of claim 1 , wherein the imprint lithography process comprises a nanoimprint lithography process.
5 . The memory cell of claim 1 , wherein the phase-change material comprises a chalcogenide.
6 . The memory cell of claim 1 , wherein the phase-change material comprises a chalcogen free material.
7 . A memory cell comprising:
a first electrode;
a second electrode; and
a phase-change material between the first electrode and the second electrode, the phase-change material having a cross-sectional area defined by an imprint lithography process.
8 . The memory cell of claim 7 , wherein the imprint lithography process comprises a step and flash imprint lithography process.
9 . The memory cell of claim 7 , wherein the imprint lithography process comprises a nanotransfer printing lithography process.
10 . The memory cell of claim 7 , wherein the imprint lithography process comprises a nanoimprint lithography process.
11 . The memory cell of claim 7 , wherein the phase-change material comprises a chalcogenide.
12 . The memory cell of claim 7 , wherein the phase-change material comprises a chalcogen free material.
13 . A memory cell comprising:
a first electrode;
a heater electrode adjacent the first electrode, the heater electrode having a cross-sectional area defined by an imprint lithography process;
a phase-change material adjacent the heater electrode; and
a second electrode adjacent the phase-change material.
14 . The memory cell of claim 13 , wherein the imprint lithography process comprises a step and flash imprint lithography process.
15 . The memory cell of claim 13 , wherein the imprint lithography process comprises a nanotransfer printing lithography process.
16 . The memory cell of claim 13 , wherein the imprint lithography process comprises a nanoimprint lithography process.
17 . The memory cell of claim 13 , wherein the phase-change material comprises a chalcogenide.
18 . The memory cell of claim 13 , wherein the phase-change material comprises a chalcogen free material.
19 . A memory device comprising:
a write pulse generator for generating a write pulse signal;
a sense amplifier for sensing a read signal;
a distribution circuit; and
a plurality of phase-change memory cells each capable of defining at least a first state and a second state, each memory cell further comprising phase-change material having a cross-sectional area defined by an imprint lithography process.
20 . The memory cell of claim 19 , wherein the imprint lithography process comprises a step and flash imprint lithography process.
21 . The memory cell of claim 19 , wherein the imprint lithography process comprises a nanotransfer printing lithography process.
22 . The memory cell of claim 19 , wherein the imprint lithography process comprises a nanoimprint lithography process.
23 . The memory cell of claim 19 , wherein the phase-change material comprises a chalcogenide.
24 . A memory device comprising:
a write pulse generator for generating a write pulse signal;
a sense amplifier for sensing a read signal;
a distribution circuit; and
a plurality of phase-change memory cells each capable of defining at least a first state and a second state, each memory cell further comprising a heater electrode having a cross-sectional area defined by an imprint lithography process.
25 . The memory cell of claim 24 , wherein the imprint lithography process comprises a step and flash imprint lithography process.
26 . The memory cell of claim 24 , wherein the imprint lithography process comprises a nanotransfer printing lithography process.
27 . The memory cell of claim 24 , wherein the imprint lithography process comprises a nanoimprint lithography process.
28 . The memory cell of claim 24 , wherein the phase-change material comprises a chalcogenide.
29 . A method for fabricating a memory cell, the method comprising:
providing a preprocessed wafer having a first electrode;
depositing an insulation material layer over the preprocessed wafer;
applying a transfer material layer over the insulation material layer;
imprinting the transfer material layer to form an opening;
etching the transfer material layer and the insulation material layer through the opening to expose the first electrode;
removing the transfer material layer;
depositing phase-change material in the opening; and
fabricating a second electrode in contact with the phase-change material.
30 . The method of claim 29 , wherein imprinting the transfer material layer comprises step and flash imprinting.
31 . The method of claim 29 , wherein imprinting the transfer material layer comprises nanotransfer printing.
32 . The method of claim 29 , wherein imprinting the transfer material layer comprises nanoimprinting.
33 . The method of claim 29 , wherein depositing the phase-change material comprises depositing a chalcogenide
34 . A method for fabricating a memory cell, the method comprising:
providing a preprocessed wafer having a first electrode;
depositing an insulation material layer over the preprocessed wafer;
applying a transfer material layer over the insulation material layer;
imprinting the transfer material layer to form an opening;
etching the transfer material layer and the insulation material layer through the opening to expose the first electrode;
removing the transfer material layer;
depositing heater material in the opening;
depositing a phase-change material layer over the heater material;
depositing an electrode material layer over the phase-change material layer; and
etching the electrode material layer and the phase-change material layer to form a second electrode and a memory storage location.
35 . The method of claim 34 , wherein imprinting the transfer material layer comprises step and flash imprinting.
36 . The method of claim 34 , wherein imprinting the transfer material layer comprises nanotransfer printing.
37 . The method of claim 34 , wherein imprinting the transfer material layer comprises nanoimprinting.
38 . The method of claim 34 , wherein depositing the phase-change material comprises depositing a chalcogenide.