Method and system for a circuit for timing sensitive applications
Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.
1. A circuit, comprising:
an input;
a first logic coupled to the input and operable to drive an input signal to a second logic;
a dummy logic coupled to the input; and
a third logic coupled to the input, wherein the output of the third logic is not coupled to the second logic, wherein the first logic is a first inverter and the third logic is a second inverter and the circuit has substantially the same input capacitance and timing delay as a baseline circuit comprising a baseline inverter with a baseline drive strength for driving a baseline capacitance load.
2. The circuit of claim 1 , wherein the first inverter has a drive strength
1
m
that of the baseline drive strength.
3. The circuit of claim 2 , wherein the dummy logic has a capacitance load
1
m
(
1
-
1
n
)
that of the baseline capacitance load.
4. The circuit of claim 3 , wherein the second inverter has a drive strength
1
mn
that of the baseline drive strength.
5. The circuit of claim 4 , wherein the second logic has a capacitance
1
m
that of the baseline capacitance.
6. The circuit of claim 5 , wherein the input signal is a clock signal.
7. The circuit of claim 3 , wherein
ⅆ
(
v
float
-
v
i
n
)
ⅆ
t
ⅆ
(
v
out
-
v
i
n
)
ⅆ
t
.
8. A method for driving an input signal received at an input, comprising:
providing the input signal to a first logic operable to drive the input signal to a second logic;
providing the input signal to a dummy logic;
providing the input signal to a third logic, wherein the output of the second inverter is not coupled to the second logic, the first logic is a first inverter and the third logic is a second inverter; and
providing substantially the same input capacitance and timing delay as a baseline circuit comprising a baseline inverter with a baseline drive strength for driving a baseline capacitance load.
9. The method of claim 8 , wherein the first inverter has a drive strength
1
m
that of the baseline drive strength.
10. The method of claim 9 , wherein the dummy logic has a capacitance load
1
m
(
1
-
1
n
)
that of the baseline capacitance load.
11. The method of claim 10 , wherein the second inverter has a drive strength
1
mn
that of the baseline drive strength.
12. The method of claim 11 , wherein
n
=
ⅆ
(
v
float
-
v
in
)
ⅆ
t
ⅆ
(
v
out
-
v
in
)
ⅆ
t
.
13. The method of claim 11 , wherein the second logic has a capacitance
1
m
that of the baseline capacitance.
14. The method of claim 13 , wherein the input signal is a clock signal.
15. A circuit, wherein the circuit has substantially the same input capacitance and timing delay as a baseline circuit comprising a baseline inverter with a baseline drive strength for driving a baseline capacitance load, the circuit comprising:
an input;
a first inverter coupled to the input and operable to drive a clock signal at the input to a logic, wherein the first inverter has a drive strength
1
m
that of the baseline drive strength;
a dummy logic coupled to the input, wherein the dummy logic has a capacitance load
1
m
(
1
-
1
n
)
that of the baseline capacitance load; and
a second inverter coupled to the input, wherein the second inverter has a drive strength
1
mn
that of the baseline drive strength and the output of the second inverter is not coupled to the logic.