Synchronous counting circuit

1. An integrated M by N bit counter, comprising:

an M by N register configured to receive and store data corresponding to at least one word, said M by N register configured to receive a set of M selectable words;

a N bit counter configured to sequentially count out a selected word of data from the M by N register; and

a control mechanism configured to include each 1 bit register contained in each selected word of the set of M selectable words stored in the M by N register into the N bit counter, thereby forming the integrated M by N counter.

2. The integrated M by N bit counter of claim 1 , wherein the control mechanism combines all 1 bit registers of the N bit counter with the storage registers of each of the set of M selectable words stored in the M by N bit counter.

3. The integrated M by N bit counter of claim 1 , wherein the N bit counter comprises at least one N-bit store element comprising one bit of an N-bit word, said store element configured to receive data over M access lines, wherein all the N-bit storage elements in an N-bit word form one of M words stored in the M by N register.

4. The integrated M by N bit counter of claim 3 , wherein the N-bit counter further comprises at least one series enable signal and at least one clock signal to enable reading data from each N-bit store element.

5. The integrated M by N bit counter of claim 4 , wherein the N-bit counter comprises a series combination of 1 bit registers contained in one of M words and each of the 1 bit registers contained in one of M words shares information and transmits a vector of data including an element of the selected word of data contributed by the 1 bit register contained in the one of M words.

6. The integrated M by N bit counter of claim 1 , wherein the M by N register receives a 1 by M select indication to select a row of words from among several words maintained in the M by N register.

7. The integrated M by N bit counter of claim 1 , wherein the N bit counter shares data stored in the M by N register, and the N-bit counter receives a control clock signal and enable signal, and produces a one dimensional array counted out therefrom.

8. The integrated M by N bit counter of claim 6 , wherein the N bit counter receives a reset signal resetting at least one data value in the N bit counter to zero.

9. An M by N bit counter, comprising:

an N-bit counter comprising a serially connected plurality of M by 1-bit counters, each M by 1-bit counter comprising a register and having an enable control feature; and

load/store control logic connecting one of M words, and further enabling register configuration of the N bit counter to include N storage registers of a selected one of M words;

wherein the load/store logic provides clock signals to the serially connected plurality of M by 1-bit counters each having an enable control feature to enable sharing of data from at least one register;

and further wherein the serially connected plurality of M by 1 bit counters receive word select signals selecting the desired word for data sharing.

10. The M by N bit counter of claim 9 , wherein each M by 1-bit counter comprises an M-bit store configured to share data across M access lines.

11. The M by N bit counter of claim 9 , wherein each M by 1-bit counter shares information and transmits a vector of data including an element of the selected word of data contributed by the M by 1 bit counter.

12. The M by N bit counter of claim 9 , wherein each M by 1-bit counter receives a series enable signal, the series enable signal enabling transmission of a vector of data including an element of the selected word of data.

13. The M by N bit counter of claim 9 , wherein a word selected using the M by 1-bit counter causes the M by 1-bit counter to count at least one bit from an N-bit store and pass a vector including the at least one bit.

14. The M by N bit counter of claim 9 , further comprising a count in mechanism configured to provide a count in to a first M by 1-bit counter.

15. An array arrangement for controlling a plurality of independently controllable circuits, comprising:

an M by N register comprising a set of M selectable words, each selectable word comprising a set of 1 bit registers, said M by N register configured to store and receive an M by 1-bit selection of data selectable from the M by N register;

an N bit counter configured to count data selected using the M by 1-bit selection; and

a control mechanism configured to include each M by 1 bit register into a serial N bit counter.

16. The array arrangement of claim 15 , wherein the control mechanism combines the 1 bit data registers of the N bit counter with data storage registers of each of M words stored in the M by N bit counter.

17. The array arrangement of claim 15 , wherein the N bit counter comprises a plurality of serially connected N M by 1 bit counters with enable control selectively enabled to count data selected using the M by 1 bit counter.

18. The array arrangement of claim 17 , wherein each M by 1 bit counter comprises a single bit M word series enabled synchronous counter having N bit store elements sharing data across M access lines.

19. The array arrangement of claim 17 , wherein the each M by 1 bit counter shares data with selected storage elements and transmits a vector quantity having at least one bit of data selected using the M by 1 bit selection.

20. The array arrangement of claim 15 , further comprising load/store logic used to selectively count out selected data using at least one of a plurality of N by 1 bit counters.

21. The array arrangement of claim 15 , wherein the M by N register receives a 1 of M select indication to select a row of words from among several words maintained in the M by N register.

22. The array arrangement of claim 15 , wherein the N bit counter shares data from the M by N register, and the N-bit counter receives a control clock signal and enable signal, and produces a one dimensional array counted out therefrom.