IP Library Granted Patent US 7,491,966
Granted Patent B2
US 7,491,966 · App. 11/157,260 · Granted Feb 17, 2009

Semiconductor substrate and process for producing it

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Quick Facts
Patent No.
US 7,491,966
App. No.
11/157,260
Granted
Feb 17, 2009
Kind
B2
Abstract

A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm 2 or less.

Claims (8)

1. A semiconductor substrate, comprising a carrier wafer and a joined layer comprising single-crystalline semiconductor material, wherein the joined layer has a thickness of 100 nm or less, has a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm 2 or less.

2. The semiconductor substrate of claim 1 , wherein the joined layer is one of silicon, strained silicon, silicon-germanium, germanium, or silicon carbide.

3. The semiconductor substrate of claim 1 , wherein the carrier wafer is a silicon wafer with an oxide layer.

4. The semiconductor substrate of claim 1 , wherein the joined layer of single-crystalline semiconductor material has a thickness of 80 nm or less.

5. The semiconductor substrate of claim 4 , wherein the joined layer of single-crystalline semiconductor material has a thickness of 50 nm or less.

6. The semiconductor substrate of claim 5 , wherein the joined layer of single-crystalline semiconductor material has a thickness of 20 nm or less.

7. The semiconductor substance of claim 1 wherein the joined layer is a semiconductor layer of a donor wafer, the semiconductor layer having had recesses on a surface thereof which is joined to a surface of the carrier wafer, the carrier wafer and joined donor wafer are thermally treated to close up the recesses at said semiconductor layer surface, forming a single crystal joined layer, and the carrier wafer and single crystal joined layer are separated along the plane of closed recesses, wherein the thickness and thickness uniformity of the joined layer are measured following joining but prior to further processing.

8. The semiconductor substance of claim 7 wherein the joined layer has a thickness of 20 nm or less.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2005
From: DANTZ, DIRK; HUBER, ANDREAS; WAHLICH, REINHOLD; MURPHY, BRIAN
To: SILTRONIC AG
Reel/Frame 016882/0033 →