Static random access memory cell using chalcogenide
View Patent ↗A static random access memory may be formed using a bitline and a bitline bar coupled to ovonic threshold switches. The ovonic threshold switches may, in turn, be coupled to cross coupled NMOS transistors. In some embodiments, a very compact static random access memory may result.
1. A static random access memory comprising:
a static random access memory cell including a chalcogenide that is always in an amorphous phase and cross coupled NMOS transistors, wherein the gate of each transistor is coupled to the drain of the other transistor, said memory cell including first and second ovonic threshold switches, said chalcogenide being part of said switches.
2. The memory of claim 1 including an ovonic threshold switch including said chalcogenide.
3. The memory of claim 2 including a phase change memory in series with said switch.
4. The memory of claim 1 wherein said transistors have a common source.
5. The memory of claim 1 wherein one transistor's gate is coupled to said first ovonic threshold switch and the other transistor's drain is coupled to said first ovonic threshold switch.
6. The memory of claim 5 including an L-shaped metal layer having opposed ends, said layer coupled to one said NMOS transistor drain on one end, a region between the ends forming the lower conductor of said first ovonic threshold switch and said layer coupled to a gate electrode of the other said NMOS transistors on the other end.
7. The memory of claim 6 including a plug from said layer to said gate electrode.
8. The memory of claim 6 including a bitline coupled to said first ovonic threshold switch and a bitline bar coupled to said second ovonic threshold switch.
9. A method comprising:
forming a static random access memory using a chalcogenide that is always in the amorphous phase;
forming said static random access memory using cross coupled NMOS transistors;
coupling the gate of each transistor to the drain of the other transistor; and
forming a first and second ovonic threshold switch and coupling the gate of one transistor to said first ovonic threshold switch and the drain of the other transistor to said first ovonic threshold switch.
10. The method of claim 9 including forming an ovonic threshold switch using said chalcogenide.
11. The method of claim 10 including forming a phase change memory in series with said ovonic threshold switch.
12. The method of claim 11 wherein a phase change memory state is determined by a trailing edge of a read or write termination cycle.
13. The method of claim 9 including forming a common source for said NMOS transistors.
14. The method of claim 9 including forming an L-shaped metal layer having opposed ends such that one end of said layer is coupled to one said NMOS transistor drain, a region between the ends forms a lower electrode of said first ovonic threshold switch and the other end of said layer is coupled to the gate electrode of the other said NMOS transistors.
15. The method of claim 14 including forming a plug from said layer to said gate electrode.
16. The method of claim 14 including coupling said first ovonic threshold switch to a first bitline and said second ovonic threshold switch to a second bitline.
17. The method of claim 9 including reading said memory by charging a pair of bitlines and then discharging one of the bitlines relative to the other.
18. The method of claim 9 including writing said memory by biasing one of said bitlines coupled to said cell higher than the other of said bitlines.