Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
View Patent ↗A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
1. A method comprising:
forming a dummy gate electrode over PMOS side of a complementary structure;
covering said dummy gate electrode with a nitride etch stop layer;
covering a gate electrode over the NMOS side with said nitride etch stop layer;
removing a portion of said nitride etch stop layer on said PMOS side while maintaining said etch stop over said NMOS side;
removing said dummy electrode and replacing said dummy electrode with a metal gate electrode; and
forming an epitaxial p-type source drain on the PMOS side.
2. The method of claim 1 including forming a raised source drain.
3. The method of claim 1 including forming a gate dielectric having a dielectric constant greater than 10.
4. The method of claim 1 including a U-shaped gate dielectric.
5. The method of claim 1 including forming said source drain of p-type doped silicon germanium.
6. The method of claim 1 including forming said nitride etch stop layer over a hard mask.
7. The method of claim 1 including forming said dummy gate electrode of polysilicon.
8. The method of claim 1 including forming a complementary metal oxide semiconductor integrated circuit.
9. The method of claim 1 including etching into a semiconductor substrate using the dummy gate electrode as a mask and depositing a boron doped silicon germanium epitaxial material to form said p-type source drain.